Abstract: A method of allocating and distributing processes to network resources. The amount of network resources is determined for each process or groups of processes to be executed on the computer network. A minimum source allocation is provided for one or more of the processes. Each of the network resources is monitored for resource use. If necessary, a resource allocator redistributes network resources in accordance with the minimum resource allocation.

Abstract: A computer system operable to provide nodes of a cluster with a quorum resource includes a network interface controller, a mass storage device, a processor, and memory. The network interface controller is operable to send messages to the nodes via a network and receive messages from the nodes via the network. The mass storage device includes storage that is used to implement the quorum resource and that is accessible by the nodes via the network interface controller. The processor is operably coupled to the network interface controller and the mass storage device. The memory is operably coupled to the processor and includes instructions, which when executed by the processor, cause the processor to process a first message requesting ownership of the quorum resource that is received from a first node of the cluster via the network interface controller.

Abstract: An improved affinity scheduling system for assigning processes to processors within a multiprocessor computer system which includes a plurality of processors and cache memories associated with each processor. The affinity scheduler affinitizes processes to processors so that processes which frequently modify the same data are affined to the same local processor—the processor whose cache memory includes the data being modified by the processes. The scheduler monitors the scheduling and execution of processes to identify processes which frequently modify data residing in the cache memory of a non-local processor. When a process is identified which requires access to data residing in the cache memory of a non-local processor with greater frequency than the process requires access to data residing in the cache memory of its affined local processor, the affinity of the process is changed to the non-local processor.

Abstract: A method and apparatus are disclosed for use on a computer network for allocating and distributing processes to network resources. The amount of network resources is determined for each process or groups of processes to be executed on the computer network. A minimum resource allocation is provided for one or more of the processes. Each of the network resources is monitored for resource use. If necessary, a resource allocator redistributes network resources in accordance with the minimum resource allocation.

Abstract: A memory management system and method that determines which page or pages in cache memory are likely to be accessed again in the near future by another transaction and designates those pages for recycling so that the pages are maintained in the cache memory for a longer period of time. That is, pages designated for recycling are maintained in the cache, while pages that are not are first replaced. According to the present application, pages in the cache that are likely to be accessed in the near future are those that are accessed by two or more different transactions during their normal residence in the cache.

Abstract: An improved affinity process scheduling method for a multiprocessor computer system, wherein a process previously executed on a processor within the computer system is affined to the processor on which it previously executed, and will be scheduled for execution by the affined processor during subsequent requests for execution of the affined process. The improved affinity process scheduling method monitors the length of time the affined process resides on the system run queue awaiting execution by its affined processor; and schedules the affined process for execution with another available processor when the length of time the affined process has been waiting for execution exceeds a predetermined "steal-age" threshold.

Abstract: A method and apparatus for enabling a physical memory larger than a corresponding virtual memory. An apparatus is disclosed that includes a processor having an address word of a predefined length, a main memory having a size larger than the addressable range of the predefined address word, and virtual memory logic for configuring the processor virtual memory to contain a subset of the main memory as resident memory and pointers to the remainder of main memory. Analogous method steps are disclosed as is dividing main memory into a plurality of buffer uniquely identifiable within the address range of the predefined address word.

Abstract: A method for assigning processes to processors within a multi-processor computer system employing a sleep/wakeup facility whereby a first process requiring information from a second process is placed into a "sleep" state by said computer system until said second process is able to provide said required information, said first process thereupon being awakened by said computer system so that said first process may continue processing with the required information. The method comprising the steps of identifying a pair of processes which frequently exchange wakeup requests, and assigning the processes within the pair of processes to the same processor within the multi-processor computer system for execution.

Abstract: A method and apparatus for providing coherency for cache data in a multiple processor system with the processors distributed among multiple independent data paths. The apparatus includes a set of cache monitors, sometimes called snoopers, associated with each cache memory. There are the same number of monitors as there are independent data paths. Thus, each cache stores cache tags that correspond to its currently encached data into each of the monitors of the set associated therewith. Thus, each cache has an monitor associated therewith which monitors each of the multiple paths for an operation at an address that corresponds to data stored in its cache. If such an access is detected by one of the set of monitors, the monitor notifies its cache so that appropriate action will be taken to ensure cache data coherency.