Abstract: The present invention provides an interface and method for synchronous data transfer between domains clocked at different frequencies. The interface includes a first latch for receiving data from a first domain clocked at one frequency when the first latch is selected and a second latch for receiving data from the first domain when the second latch is selected. A third latch is provided for transferring data from either the first latch or the second latch to the second domain when the second domain is clocked.

Abstract: A system and method of generating a clock signal as a function of a system clock. A plurality of overlapping phases are generated and two or more of the overlapping phases are combined to form the clock signal.

Abstract: A clock distribution system minimizes clock skew in the distribution of clock signals to individual circuit board components in a highly synchronous, high speed computer system. The clock system includes an optical subsystem and an electrical subsystem. The optical subsystem utilizes multiple lasers and an n.times.n passive star coupler to introduce clock redundancy into the system. The lengths of the optical distribution fibers are controlled such that they are of equivalent optical path length. Once delivered to the logic assemblies, the optical clock signals are converted into equivalent electrical clock signals. The electrical subsystem then distributes the converted electrical clock signals to individual circuit board components over equalized fanout paths such that the skew as seen by the individual components is minimized. The system also compensates for skew introduced by the receiver and fanout electronics by tuning the length of the fiber.

Abstract: Logic unit cells are disclosed, consisting of an array of high speed logic gates, the outputs of which are wired together and coupled to a low power driver. High speed and switching rates are achieved by using very fast logic gates which have no gain and make use of a wired logic function in order to effect two levels of logic without adding the propagation delay through another logic gate. These arrays of logic gates are coupled to drivers which restore logic levels and provide the necessary power for driving interconnect capacitances while consuming and dissipating a minimum of power in the process. Another logic circuit discloses an array of logic gates as inputs to another logic gate, the individual gates consisting of gallium arsenide components and having drivers built into the output stage of each gate.