Patents by Inventor Veronique C. Macary

Veronique C. Macary has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7795674
    Abstract: An embodiment of an N-channel device has a lightly doped substrate in which adjacent or spaced-apart P and N wells are provided. A lateral isolation wall surrounds at least a portion of the substrate and is spaced apart from the wells. A first gate overlies the P well or the substrate between the wells or partly both. A second gate, spaced apart from the first gate, overlies the N-well. A body contact to the substrate is spaced apart from the isolation wall by a first distance within the space charge region of the substrate to isolation wall PN junction. When the body contact is connected to the second gate, a predetermined static bias Vg2 is provided to the second gate, depending upon the isolation wall bias (Vbias) and the first distance.
    Type: Grant
    Filed: September 16, 2009
    Date of Patent: September 14, 2010
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Hongning Yang, Veronique C. Macary, Won Gi Min, Jiang-Kai Zuo
  • Patent number: 7795702
    Abstract: Embodiments of microelectronic assemblies are provided. First and second semiconductor devices are formed over a substrate having a first dopant type at a first concentration. First and second buried regions having a second dopant type are formed respectively below the first and second semiconductor devices with a gap therebetween. At least one well region is formed over the substrate and between the first and second semiconductor devices. A barrier region having the first dopant type at a second concentration is formed between and adjacent to the first and second buried regions such that at least a portion of the barrier region extends a depth from the first and second semiconductor devices that is greater or equal to the depth of the buried regions.
    Type: Grant
    Filed: March 4, 2010
    Date of Patent: September 14, 2010
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Won Gi Min, Veronique C. Macary, Jiang-Kai Zuo
  • Patent number: 7776700
    Abstract: An N-channel device (40, 60) is described having a very lightly doped substrate (42) in which spaced-apart P (46) and N (44) wells are provided, whose lateral edges (461, 45) extending to the surface (47). The gate (56) overlies the surface (47) between the P (46) and N (44) wells. The P-well edge (461) adjacent the source (50) is substantially aligned with the left gate edge (561). The N-well edge (45) lies at or within the right gate edge (562), which is spaced a first distance (471) from the drain (48). The N-well (44) desirably includes a heavier doped region (62) in ohmic contact with the drain (48) and with its left edge (621) located about half way between the right gate edge (562) and the drain (48). A HALO implant pocket (52) is provided underlying the left gate edge (561) using the gate (56) as a mask. The resulting device (40, 60) operates at higher voltage with lower Rdson, less HCI and very low off-state leakage. P and N dopants are interchanged to provide P-channel devices.
    Type: Grant
    Filed: January 4, 2007
    Date of Patent: August 17, 2010
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Hongning Yang, Veronique C. Macary, Jiang-Kai Zuo
  • Publication number: 20100164056
    Abstract: Embodiments of microelectronic assemblies are provided. First and second semiconductor devices are formed over a substrate having a first dopant type at a first concentration. First and second buried regions having a second dopant type are formed respectively below the first and second semiconductor devices with a gap therebetween. At least one well region is formed over the substrate and between the first and second semiconductor devices. A barrier region having the first dopant type at a second concentration is formed between and adjacent to the first and second buried regions such that at least a portion of the barrier region extends a depth from the first and second semiconductor devices that is greater or equal to the depth of the buried regions.
    Type: Application
    Filed: March 4, 2010
    Publication date: July 1, 2010
    Applicant: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Won Gi Min, Veronique C. Macary, Jiang-Kai Zuo
  • Patent number: 7700405
    Abstract: A method for forming a microelectronic assembly and a microelectronic assembly are provided. First and second semiconductor devices (72) are formed over a substrate (20) having a first dopant type at a first concentration. First and second buried regions (28) having a second dopant type are formed respectively below the first and second semiconductor devices with a gap (34) therebetween. At least one well region (64, 70) is formed over the substrate and between the first and second semiconductor devices. A barrier region (48) having the first dopant type at a second concentration is formed between and adjacent to the first and second buried regions such that at least a portion of the barrier region extends a depth (82) from the first and second semiconductor devices that is greater or equal to the depth of the buried regions.
    Type: Grant
    Filed: February 28, 2007
    Date of Patent: April 20, 2010
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Won Gi Min, Veronique C. Macary, Jiang-Kai Zuo
  • Publication number: 20100025765
    Abstract: An embodiment of an N-channel device has a lightly doped substrate in which adjacent or spaced-apart P and N wells are provided. A lateral isolation wall surrounds at least a portion of the substrate and is spaced apart from the wells. A first gate overlies the P well or the substrate between the wells or partly both. A second gate, spaced apart from the first gate, overlies the N-well. A body contact to the substrate is spaced apart from the isolation wall by a first distance within the space charge region of the substrate to isolation wall PN junction. When the body contact is connected to the second gate, a predetermined static bias Vg2 is provided to the second gate, depending upon the isolation wall bias (Vbias) and the first distance.
    Type: Application
    Filed: September 16, 2009
    Publication date: February 4, 2010
    Applicant: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Hongning Yang, Veronique C. Macary, Won Gi Min, Jiang-Kai Zuo
  • Patent number: 7608513
    Abstract: An N-channel device (40, 60) is described having a lightly doped substrate (42, 42?) in which adjacent or spaced-apart P (46, 46?) and N (44) wells are provided. A lateral isolation wall (76) surrounds at least a portion of the substrate (42, 42?) and is spaced apart from the wells (46, 46?, 44). A first gate (G1) (56) overlies the P (46) well or the substrate (42?) between the wells (46?, 44) or partly both. A second gate (G2) (66), spaced apart from G1 (56), overlies the N-well (44). A body contact (74) to the substrate (42, 42?) is spaced apart from the isolation wall (76) by a first distance (745) within the space charge region of the substrate (42, 42?) to isolation wall (76) PN junction. When the body contact (74) is connected to G2 (66), a predetermined static bias Vg2 is provided to G2 (66) depending upon the isolation wall bias (Vbias) and the first distance (745). The resulting device (40, 60) operates at higher voltage with lower Rdson and less HCI.
    Type: Grant
    Filed: January 25, 2007
    Date of Patent: October 27, 2009
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Hongning Yang, Veronique C. Macary, Won Gi Min, Jiang-Kai Zuo
  • Publication number: 20080203519
    Abstract: A method for forming a microelectronic assembly and a microelectronic assembly are provided. First and second semiconductor devices (72) are formed over a substrate (20) having a first dopant type at a first concentration. First and second buried regions (28) having a second dopant type are formed respectively below the first and second semiconductor devices with a gap (34) therebetween. At least one well region (64, 70) is formed over the substrate and between the first and second semiconductor devices. A barrier region (48) having the first dopant type at a second concentration is formed between and adjacent to the first and second buried regions such that at least a portion of the barrier region extends a depth (82) from the first and second semiconductor devices that is greater or equal to the depth of the buried regions.
    Type: Application
    Filed: February 28, 2007
    Publication date: August 28, 2008
    Applicant: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Won Gi Min, Veronique C. Macary, Jiang-Kai Zuo
  • Publication number: 20080182394
    Abstract: An N-channel device (40, 60) is described having a lightly doped substrate (42, 42?) in which adjacent or spaced-apart P (46, 46?) and N (44) wells are provided. A lateral isolation wall (76) surrounds at least a portion of the substrate (42, 42?) and is spaced apart from the wells (46, 46?, 44). A first gate (G1) (56) overlies the P (46) well or the substrate (42?) between the wells (46?, 44) or partly both. A second gate (G2) (66), spaced apart from G1 (56), overlies the N-well (44). A body contact (74) to the substrate (42, 42?) is spaced apart from the isolation wall (76) by a first distance (745) within the space charge region of the substrate (42, 42?) to isolation wall (76) PN junction. When the body contact (74) is connected to G2 (66), a predetermined static bias Vg2 is provided to G2 (66) depending upon the isolation wall bias (Vbias) and the first distance (745). The resulting device (40, 60) operates at higher voltage with lower Rdson and less HCI.
    Type: Application
    Filed: January 25, 2007
    Publication date: July 31, 2008
    Inventors: Hongning Yang, Veronique C. Macary, Won Gi Min, Jiang-Kai Zuo
  • Publication number: 20080166849
    Abstract: An N-channel device (40, 60) is described having a very lightly doped substrate (42) in which spaced-apart P (46) and N (44) wells are provided, whose lateral edges (461, 45) extending to the surface (47). The gate (56) overlies the surface (47) between the P (46) and N (44) wells. The P-well edge (461) adjacent the source (50) is substantially aligned with the left gate edge (561). The N-well edge (45) lies at or within the right gate edge (562), which is spaced a first distance (471) from the drain (48). The N-well (44) desirably includes a heavier doped region (62) in ohmic contact with the drain (48) and with its left edge (621) located about half way between the right gate edge (562) and the drain (48). A HALO implant pocket (52) is provided underlying the left gate edge (561) using the gate (56) as a mask. The resulting device (40, 60) operates at higher voltage with lower Rdson, less HCI and very low off-state leakage. P and N dopants are interchanged to provide P-channel devices.
    Type: Application
    Filed: January 4, 2007
    Publication date: July 10, 2008
    Inventors: Hongning Yang, Veronique C. Macary, Jiang-Kai Zuo
  • Patent number: 6667500
    Abstract: An LDMOS field effect transistor (80) provides protection against the inadvertent reversal of polarity of voltage applied across the device. To protect an N-channel device, a floating P-type blocking region (82) is provided surrounding the drain region (32). The blocking region (82) is spaced apart from a body region (28) that forms the diffused channel (34) of the transistor (80). A first gate electrode (36) controls the conductivity of the diffused channel (34) and a second gate electrode (84) controls the conductivity of the surface (35) of the blocking region (82).
    Type: Grant
    Filed: April 19, 2002
    Date of Patent: December 23, 2003
    Assignee: Motorola, Inc.
    Inventors: Thierry Sicard, Veronique C. Macary
  • Publication number: 20030008443
    Abstract: An LDMOS field effect transistor (80) provides protection against the inadvertent reversal of polarity of voltage applied across the device. To protect an N-channel device, a floating P-type blocking region (82) is provided surrounding the drain region (32). The blocking region (82) is spaced apart from a body region (28) that forms the diffused channel (34) of the transistor (80). A first gate electrode (36) controls the conductivity of the diffused channel (34) and a second gate electrode (84) controls the conductivity of the surface (35) of the blocking region (82).
    Type: Application
    Filed: April 19, 2002
    Publication date: January 9, 2003
    Inventors: Thierry Sicard, Veronique C. Macary
  • Patent number: 6413806
    Abstract: An LDMOS field effect transistor (80) provides protection against the inadvertent reversal of polarity of voltage applied across the device. To protect an N-channel device, a floating P-type blocking region (82) is provided surrounding the drain region (32). The blocking region (82) is spaced apart from a body region (28) that forms the diffused channel (34) of the transistor (80). A first gate electrode (36) controls the conductivity of the diffused channel (34) and a second gate electrode (84) controls the conductivity of the surface (35) of the blocking region (82).
    Type: Grant
    Filed: February 23, 2000
    Date of Patent: July 2, 2002
    Assignee: Motorola, Inc.
    Inventors: Thierry Sicard, Veronique C. Macary
  • Publication number: 20020045301
    Abstract: An LDMOS field effect transistor (80) provides protection against the inadvertent reversal of polarity of voltage applied across the device. To protect an N-channel device, a floating P-type blocking region (82) is provided surrounding the drain region (32). The blocking region (82) is spaced apart from a body region (28) that forms the diffused channel (34) of the transistor (80). A first gate electrode (36) controls the conductivity of the diffused channel (34) and a second gate electrode (84) controls the conductivity of the surface (35) of the blocking region (82).
    Type: Application
    Filed: February 23, 2000
    Publication date: April 18, 2002
    Inventors: Thierry Sicard, Veronique C. Macary