Patents by Inventor Vesselina K. Papazova
Vesselina K. Papazova has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10628314Abstract: Embodiments of the present invention are directed to managing a shared high-level cache for dual clusters of fully connected integrated circuit multiprocessors. An example of a computer-implemented method includes: providing a drawer comprising a plurality of clusters, each of the plurality of clusters comprising a plurality of processors; providing a shared cache integrated circuit to manage a shared cache memory among the plurality of clusters; receiving, by the shared cache integrated circuit, an operation of one of a plurality of operation types from one of the plurality of processors; and processing, by the shared cache integrated circuit, the operation based at least in part on the operation type of the operation according to a set of rules for processing the operation type.Type: GrantFiled: November 1, 2017Date of Patent: April 21, 2020Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Michael A. Blake, Timothy C. Bronson, Pak-kin Mak, Vesselina K. Papazova, Robert J. Sonnelitter, III
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Patent number: 10628313Abstract: Embodiments of the present invention are directed to managing a shared high-level cache for dual clusters of fully connected integrated circuit multiprocessors. An example of a computer-implemented method includes: providing a drawer comprising a plurality of clusters, each of the plurality of clusters comprising a plurality of processors; providing a shared cache integrated circuit to manage a shared cache memory among the plurality of clusters; receiving, by the shared cache integrated circuit, an operation of one of a plurality of operation types from one of the plurality of processors; and processing, by the shared cache integrated circuit, the operation based at least in part on the operation type of the operation according to a set of rules for processing the operation type.Type: GrantFiled: May 26, 2017Date of Patent: April 21, 2020Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Michael A. Blake, Timothy C. Bronson, Pak-kin Mak, Vesselina K. Papazova, Robert J. Sonnelitter, III
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Patent number: 10572385Abstract: A cache coherency management facility to reduce latency in granting exclusive access to a cache in certain situations. A node requests exclusive access to a cache line of the cache. The node is in one region of nodes of a plurality of regions of nodes. The one region of nodes includes the node requesting exclusive access and another node of the computing environment, in which the node and the another node are local to one another as defined by a predetermined criteria. The node requesting exclusive access checks a locality cache coherency state of the another node, the locality cache coherency state being specific to the another node and indicating whether the another node has access to the cache line. Based on the checking indicating that the another node has access to the cache line, a determination is made that the node requesting exclusive access is to be granted exclusive access to the cache line.Type: GrantFiled: December 8, 2017Date of Patent: February 25, 2020Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Timothy C. Bronson, Garrett M. Drapala, Pak-Kin Mak, Vesselina K. Papazova, Hanno Ulrich
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Patent number: 10489294Abstract: Embodiments of the present invention are directed to hot cache line arbitration. An example of a computer-implemented method for hot cache line arbitration includes receiving a request for exclusive access to a cache line from a requestor of a drawer in a processing system. The method further includes bringing the cache line to a local cache of the drawer. The method further includes invalidating copies of the cache line in the processing system. The method further includes loading a remote fetch address register (RFAR) controller on other drawers in the processing system, wherein the RFAR comprises a local pending flag and a remote pending flag.Type: GrantFiled: April 5, 2017Date of Patent: November 26, 2019Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Michael A. Blake, Rebecca M. Gott, Pak-Kin Mak, Vesselina K. Papazova
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Patent number: 10489292Abstract: Embodiments of the present invention are directed to a computer-implemented method for ownership tracking updates across multiple simultaneous operations. A non-limiting example of the computer-implemented method includes receiving, by a cache directory control circuit, a message to update a cache directory entry. The method further includes, in response, updating, by the cache directory control circuit, the cache directory entry, and generating a reverse compare signal including an updated ownership vector of a memory line corresponding to the cache directory entry. The method further includes sending the reverse compare signal to a cache controller associated with the cache directory entry.Type: GrantFiled: November 20, 2017Date of Patent: November 26, 2019Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Michael A. Blake, Timothy C. Bronson, Ashraf ElSharif, Kenneth D. Klapproth, Vesselina K. Papazova, Guy G. Tracy
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Patent number: 10482015Abstract: Embodiments of the present invention are directed to a computer-implemented method for ownership tracking updates across multiple simultaneous operations. A non-limiting example of the computer-implemented method includes receiving, by a cache directory control circuit, a message to update a cache directory entry. The method further includes, in response, updating, by the cache directory control circuit, the cache directory entry, and generating a reverse compare signal including an updated ownership vector of a memory line corresponding to the cache directory entry. The method further includes sending the reverse compare signal to a cache controller associated with the cache directory entry.Type: GrantFiled: May 18, 2017Date of Patent: November 19, 2019Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Michael A. Blake, Timothy C. Bronson, Ashraf ElSharif, Kenneth D. Klapproth, Vesselina K. Papazova, Guy G. Tracy
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Patent number: 10380020Abstract: Embodiments include methods, systems and computer program products method for maintaining ordered memory access with parallel access data streams associated with a distributed shared memory system. The computer-implemented method includes performing, by a first cache, a key check, the key check being associated with a first ordered data store. A first memory node signals that the first memory node is ready to begin pipelining of a second ordered data store into the first memory node to an input/output (I/O) controller. A second cache returns a key response to the first cache indicating that the pipelining of the second ordered data store can proceed. The first memory node sends a ready signal indicating that the first memory node is ready to continue pipelining of the second ordered data store into the first memory node to the I/O controller, wherein the ready signal is triggered by receipt of the key response.Type: GrantFiled: July 17, 2017Date of Patent: August 13, 2019Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Ekaterina M. Ambroladze, Timothy C. Bronson, Matthias Klein, Pak-kin Mak, Vesselina K. Papazova, Robert J. Sonnelitter, III, Lahiruka S. Winter
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Patent number: 10339064Abstract: Embodiments of the present invention are directed to hot cache line arbitration. An example of a computer-implemented method for hot cache line arbitration includes detecting, by a processing device, a hot cache line scenario. The computer-implemented method further includes tracking, by the processing device, hot cache line requests from requesters to determine subsequent satisfaction of the requests. The computer-implemented method further includes facilitating, by the processing device, servicing of the requests according to hierarchy of the requestors.Type: GrantFiled: March 29, 2017Date of Patent: July 2, 2019Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Michael A. Blake, Timothy C. Bronson, Jason D. Kohl, Pak-Kin Mak, Vesselina K. Papazova
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Publication number: 20190018775Abstract: Embodiments include methods, systems and computer program products method for maintaining ordered memory access with parallel access data streams associated with a distributed shared memory system. The computer-implemented method includes performing, by a first cache, a key check, the key check being associated with a first ordered data store. A first memory node signals that the first memory node is ready to begin pipelining of a second ordered data store into the first memory node to an input/output (I/O) controller. A second cache returns a key response to the first cache indicating that the pipelining of the second ordered data store can proceed. The first memory node sends a ready signal indicating that the first memory node is ready to continue pipelining of the second ordered data store into the first memory node to the I/O controller, wherein the ready signal is triggered by receipt of the key response.Type: ApplicationFiled: July 17, 2017Publication date: January 17, 2019Inventors: Ekaterina M. Ambroladze, Timothy C. Bronson, Matthias Klein, Pak-kin Mak, Vesselina K. Papazova, Robert J. Sonnelitter, III, Lahiruka S. Winter
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Publication number: 20180341587Abstract: Embodiments of the present invention are directed to managing a shared high-level cache for dual clusters of fully connected integrated circuit multiprocessors. An example of a computer-implemented method includes: providing a drawer comprising a plurality of clusters, each of the plurality of clusters comprising a plurality of processors; providing a shared cache integrated circuit to manage a shared cache memory among the plurality of clusters; receiving, by the shared cache integrated circuit, an operation of one of a plurality of operation types from one of the plurality of processors; and processing, by the shared cache integrated circuit, the operation based at least in part on the operation type of the operation according to a set of rules for processing the operation type.Type: ApplicationFiled: November 1, 2017Publication date: November 29, 2018Inventors: Michael A. Blake, Timothy C. Bronson, Pak-kin Mak, Vesselina K. Papazova, Robert J. Sonnelitter, III
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Publication number: 20180341586Abstract: Embodiments of the present invention are directed to managing a shared high-level cache for dual clusters of fully connected integrated circuit multiprocessors. An example of a computer-implemented method includes: providing a drawer comprising a plurality of clusters, each of the plurality of clusters comprising a plurality of processors; providing a shared cache integrated circuit to manage a shared cache memory among the plurality of clusters; receiving, by the shared cache integrated circuit, an operation of one of a plurality of operation types from one of the plurality of processors; and processing, by the shared cache integrated circuit, the operation based at least in part on the operation type of the operation according to a set of rules for processing the operation type.Type: ApplicationFiled: May 26, 2017Publication date: November 29, 2018Inventors: Michael A. Blake, Timothy C. Bronson, Pak-kin Mak, Vesselina K. Papazova, Robert J. Sonnelitter, III
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Publication number: 20180336135Abstract: Embodiments of the present invention are directed to a computer-implemented method for ownership tracking updates across multiple simultaneous operations. A non-limiting example of the computer-implemented method includes receiving, by a cache directory control circuit, a message to update a cache directory entry. The method further includes, in response, updating, by the cache directory control circuit, the cache directory entry, and generating a reverse compare signal including an updated ownership vector of a memory line corresponding to the cache directory entry. The method further includes sending the reverse compare signal to a cache controller associated with the cache directory entry.Type: ApplicationFiled: November 20, 2017Publication date: November 22, 2018Inventors: Michael A. Blake, Timothy C. Bronson, Ashraf ElSharif, Kenneth D. Klapproth, Vesselina K. Papazova, Guy G. Tracy
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Publication number: 20180336134Abstract: Embodiments of the present invention are directed to a computer-implemented method for ownership tracking updates across multiple simultaneous operations. A non-limiting example of the computer-implemented method includes receiving, by a cache directory control circuit, a message to update a cache directory entry. The method further includes, in response, updating, by the cache directory control circuit, the cache directory entry, and generating a reverse compare signal including an updated ownership vector of a memory line corresponding to the cache directory entry. The method further includes sending the reverse compare signal to a cache controller associated with the cache directory entry.Type: ApplicationFiled: May 18, 2017Publication date: November 22, 2018Inventors: Michael A. Blake, Timothy C. Bronson, Ashraf ElSharif, Kenneth D. Klapproth, Vesselina K. Papazova, Guy G. Tracy
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Publication number: 20180293172Abstract: Embodiments of the present invention are directed to hot cache line arbitration. An example of a computer-implemented method for hot cache line arbitration includes receiving a request for exclusive access to a cache line from a requestor of a drawer in a processing system. The method further includes bringing the cache line to a local cache of the drawer. The method further includes invalidating copies of the cache line in the processing system. The method further includes loading a remote fetch address register (RFAR) controller on other drawers in the processing system, wherein the RFAR comprises a local pending flag and a remote pending flag.Type: ApplicationFiled: April 5, 2017Publication date: October 11, 2018Inventors: Michael A. Blake, Rebecca M. Gott, Pak-Kin Mak, Vesselina K. Papazova
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Publication number: 20180285277Abstract: Embodiments of the present invention are directed to hot cache line arbitration. An example of a computer-implemented method for hot cache line arbitration includes detecting, by a processing device, a hot cache line scenario. The computer-implemented method further includes tracking, by the processing device, hot cache line requests from requesters to determine subsequent satisfaction of the requests. The computer-implemented method further includes facilitating, by the processing device, servicing of the requests according to hierarchy of the requestors.Type: ApplicationFiled: March 29, 2017Publication date: October 4, 2018Inventors: Michael A. Blake, Timothy C. Bronson, Jason D. Kohl, Pak-Kin Mak, Vesselina K. Papazova
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Publication number: 20180101474Abstract: A cache coherency management facility to reduce latency in granting exclusive access to a cache in certain situations. A node requests exclusive access to a cache line of the cache. The node is in one region of nodes of a plurality of regions of nodes. The one region of nodes includes the node requesting exclusive access and another node of the computing environment, in which the node and the another node are local to one another as defined by a predetermined criteria. The node requesting exclusive access checks a locality cache coherency state of the another node, the locality cache coherency state being specific to the another node and indicating whether the another node has access to the cache line. Based on the checking indicating that the another node has access to the cache line, a determination is made that the node requesting exclusive access is to be granted exclusive access to the cache line.Type: ApplicationFiled: December 8, 2017Publication date: April 12, 2018Inventors: Timothy C. Bronson, Garrett M. Drapala, Pak-Kin Mak, Vesselina K. Papazova, Hanno Ulrich
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Patent number: 9852071Abstract: A cache coherency management facility to reduce latency in granting exclusive access to a cache in certain situations. A node requests exclusive access to a cache line of the cache. The node is in one region of nodes of a plurality of regions of nodes. The one region of nodes includes the node requesting exclusive access and another node of the computing environment, in which the node and the another node are local to one another as defined by a predetermined criteria. The node requesting exclusive access checks a locality cache coherency state of the another node, the locality cache coherency state being specific to the another node and indicating whether the another node has access to the cache line. Based on the checking indicating that the another node has access to the cache line, a determination is made that the node requesting exclusive access is to be granted exclusive access to the cache line.Type: GrantFiled: October 20, 2014Date of Patent: December 26, 2017Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Timothy C. Bronson, Garrett M. Drapala, Pak-kin Mak, Vesselina K. Papazova, Hanno Ulrich
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Patent number: 9798663Abstract: A cache coherency management facility to reduce latency in granting exclusive access to a cache in certain situations. A node requests exclusive access to a cache line of the cache. The node is in one region of nodes of a plurality of regions of nodes. The one region of nodes includes the node requesting exclusive access and another node of the computing environment, in which the node and the another node are local to one another as defined by a predetermined criteria. The node requesting exclusive access checks a locality cache coherency state of the another node, the locality cache coherency state being specific to the another node and indicating whether the another node has access to the cache line. Based on the checking indicating that the another node has access to the cache line, a determination is made that the node requesting exclusive access is to be granted exclusive access to the cache line.Type: GrantFiled: September 7, 2015Date of Patent: October 24, 2017Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Timothy C. Bronson, Garrett M. Drapala, Pak-kin Mak, Vesselina K. Papazova, Hanno Ulrich
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Patent number: 9678873Abstract: In one embodiment, a computer-implemented method includes detecting a cache miss for a cache line. A resource is reserved on each of one or more remote computing nodes, responsive to the cache miss. A request for a state of the cache line on the one or more remote computing nodes is broadcast to the one or more remote computing nodes, responsive to the cache miss. A resource credit is received from a first remote computing node of the one or more remote computing nodes, responsive to the request. The resource credit indicates that the first remote computing node will not participate in completing the request. The resource on the first remote computing node is released, responsive to receiving the resource credit from the first remote computing node.Type: GrantFiled: February 13, 2015Date of Patent: June 13, 2017Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Garrett M. Drapala, Vesselina K. Papazova, Robert J. Sonnelitter, III
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Patent number: 9594646Abstract: Embodiments relate to reestablishing synchronization across multiple channels in a memory system. One aspect is a computer implemented method that includes receiving an out-of-synchronization indication associated with at least one of a plurality of channels in the memory system. A memory control unit in communication with the channels performs a first stage of reestablishing synchronization that includes selectively stopping new traffic on the plurality of channels, waiting for a first time period to expire, resuming traffic on the plurality of channels based on the first time period expiring, and verifying that synchronization is reestablished for a second time period.Type: GrantFiled: August 31, 2016Date of Patent: March 14, 2017Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Glenn D. Gilda, Patrick J. Meaney, Vesselina K. Papazova, John S. Dodson