Patents by Inventor Viacheslav DUBEYKO
Viacheslav DUBEYKO has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 12210877Abstract: The present disclosure describes techniques for offloading computation based on an extended instruction set architecture (ISA). The extended ISA may be created based on identifying functions executed multiple times by a central processing unit (CPU). The extended ISA may comprise hashes corresponding to the functions and identifiers of extended operations associated with the functions. The extended operations may be converted from original operations of the functions. The extended operations may be executable by a storage device. The storage device may be associated with at least one computational core. Code may be synthesized based at least in part on the extended ISA. Computation of the synthesized code may be offloaded into the storage device.Type: GrantFiled: March 7, 2023Date of Patent: January 28, 2025Assignees: Lemon Inc., Beijing Youzhuju Network Technology Co., Ltd.Inventors: Viacheslav Dubeyko, Jian Wang
-
Patent number: 12182065Abstract: Techniques for improving performance of file system operations are provided. Dirty memory pages may be copied from a file system into a memory associated with a first hardware accelerator. Content of the memory pages may be compressed by one or more cores of the hardware accelerator. The compressed data may be compacted into a payload area of at least one log. Metadata of the at least one log may be prepared by the one or more cores of the hardware accelerator. The at least one log may be flushed into a storage device. A read operation may be performed on the at least one log. On a read path, in response to determining that a size of data from a plurality of logs is greater than a predetermined threshold, a new log may be created by combining the data using compression by a second hardware accelerator.Type: GrantFiled: April 11, 2023Date of Patent: December 31, 2024Assignees: Lemon Inc., Beijing Youzhuju Network Technology Co., Ltd.Inventors: Viacheslav Dubeyko, Jian Wang
-
Patent number: 12164920Abstract: The present disclosure describes techniques for offloading data processing and knowledge synthesis. A set of flags may indicate information about the memory pages in a first memory and may be manageable by at least one central processing unit (CPU). A memory page may be flushed to a second memory if the memory page is associated with a first flag. The first flag may indicate that the memory page is ready to be flushed to the second memory. The second memory may be configured to store a sequence of states of each of the memory pages. Data patterns and relations among the data patterns may be determined by data processing units (DPUs) based on the sequence of states of each of the memory pages. A knowledge base may be built in a third memory based on the data patterns and the relations among the data patterns.Type: GrantFiled: November 9, 2022Date of Patent: December 10, 2024Assignees: Lemon Inc., Beijing Youzhuju Network Technology Co. Ltd.Inventors: Viacheslav Dubeyko, Jian Wang
-
Patent number: 12164482Abstract: The present disclosure describes techniques for improving data processing. At least one transaction may be generated by a file system driver associated with a host. Each transaction comprises logical block addresses (LBAs) and information associated with at least one function. The at least one transaction may be journaled into a computational storage for offloading data processing from the host to the computational storage. The computational storage comprises a persistent memory and at least one field-programmable gate array (FPGA) core. The offloading of the data processing comprises offloading journal replay operations to the computational storage. The journal replay operations comprise applying the at least one function to at least one subset of the LBAs by the at least one FPGA core.Type: GrantFiled: May 6, 2022Date of Patent: December 10, 2024Assignee: Lemon Inc.Inventors: Viacheslav Dubeyko, Jian Wang
-
Patent number: 12141123Abstract: System and method of verifying validity of a metadata modification request to prevent improper metadata operations. During initialization of a volume in a storage device and once a metadata area is reserved for a metadata structure, information characterizing the metadata structure and metadata area is stored in the storage device, which may be in the form of an area legend composed of descriptors such as a magic signature, a node size, a clump size of reservation, and extent of the metadata area. Responsive to a request for operating on metadata, relevant information provided in the request is verified against the stored characteristic information. If the verification discovers an inconsistency between the information provided in the request and the stored characteristic information, the request modification is treated as invalid and blocked from operation.Type: GrantFiled: May 13, 2022Date of Patent: November 12, 2024Assignee: Sandisk Technologies, Inc.Inventors: Viacheslav Dubeyko, Adam Manzanares
-
Patent number: 12118397Abstract: The present disclosure describes techniques for accelerating data processing by offloading thread computation. An application may be started based on creating and executing a process by a host, the process associated with a plurality of threads. Creating a plurality of computation threads on a storage device may be requested based on determining that the storage device represents a computational storage. The plurality of computation threads may be created based on preloading a plurality of libraries in the storage device. The plurality of libraries may comprise executable codes associated with the plurality of threads. Data processing associated with the plurality of threads may be offloaded to the storage device using the plurality of computation threads. Activities associated with the plurality of computation threads may be managed by the process.Type: GrantFiled: September 15, 2022Date of Patent: October 15, 2024Assignees: Lemon Inc., Beijing Youzhuju Network Technology Co. Ltd.Inventors: Viacheslav Dubeyko, Jian Wang
-
Publication number: 20240152358Abstract: The present disclosure describes techniques for offloading data processing and knowledge synthesis. A set of flags may indicate information about the memory pages in a first memory and may be manageable by at least one central processing unit (CPU). A memory page may be flushed to a second memory if the memory page is associated with a first flag. The first flag may indicate that the memory page is ready to be flushed to the second memory. The second memory may be configured to store a sequence of states of each of the memory pages. Data patterns and relations among the data patterns may be determined by data processing units (DPUs) based on the sequence of states of each of the memory pages. A knowledge base may be built in a third memory based on the data patterns and the relations among the data patterns.Type: ApplicationFiled: November 9, 2022Publication date: May 9, 2024Inventors: Viacheslav Dubeyko, Jian Wang
-
Publication number: 20240095076Abstract: The present disclosure describes techniques for accelerating data processing by offloading thread computation. An application may be started based on creating and executing a process by a host, the process associated with a plurality of threads. Creating a plurality of computation threads on a storage device may be requested based on determining that the storage device represents a computational storage. The plurality of computation threads may be created based on preloading a plurality of libraries in the storage device. The plurality of libraries may comprise executable codes associated with the plurality of threads. Data processing associated with the plurality of threads may be offloaded to the storage device using the plurality of computation threads. Activities associated with the plurality of computation threads may be managed by the process.Type: ApplicationFiled: September 15, 2022Publication date: March 21, 2024Inventors: Viacheslav Dubeyko, Jian Wang
-
Patent number: 11907564Abstract: A method and system for initiating a garbage collection request. Historical data representative of a level of initiated I/O requests is acquired. A first operational state and a second operational state are determined based on the historical data. The first operational state and second operational state are expressed in an indication of the level of initiated I/O requests to be processed. A number of currently initiated I/O requests is acquired. A determination is made as to whether the number of currently initiated I/O requests is indicative of the first operational state or the second operational state. If the computer system is in the first operational state, the garbage collection request is initiated.Type: GrantFiled: August 3, 2021Date of Patent: February 20, 2024Assignee: YADRO INTERNATIONAL LTD.Inventor: Viacheslav Dubeyko
-
Patent number: 11899639Abstract: A first combined key may be generated based on a geographic location, a first time, and a first user that are associated with a first event. The first combined key and first data indicating the first event may be stored in a database, the first combined key configured to identify the first data. A second combined key may be generated based on the geographic location, a second time, and a second user that are associated with a second event. The second combined key and second data indicating the second event may be stored in the database, the second combined key configured to identify the second data. A set of events associated with the geographic location and comprising the first event and the second event may be presented by retrieving the first data and the second data using the first combined key and the second combined key, respectively.Type: GrantFiled: July 29, 2022Date of Patent: February 13, 2024Assignees: Lemon Inc., Beijing Youzhuju Network Technology Co., Ltd.Inventors: Viacheslav Dubeyko, Jian Wang
-
Publication number: 20240037080Abstract: A first combined key may be generated based on a geographic location, a first time, and a first user that are associated with a first event. The first combined key and first data indicating the first event may be stored in a database, the first combined key configured to identify the first data. A second combined key may be generated based on the geographic location, a second time, and a second user that are associated with a second event. The second combined key and second data indicating the second event may be stored in the database, the second combined key configured to identify the second data. A set of events associated with the geographic location and comprising the first event and the second event may be presented by retrieving the first data and the second data using the first combined key and the second combined key, respectively.Type: ApplicationFiled: July 29, 2022Publication date: February 1, 2024Inventors: Viacheslav Dubeyko, Jian Wang
-
Publication number: 20230401096Abstract: A storage system includes a host device and a heterogeneous memory pool. The host device includes an application and a memory allocator stored thereon. The heterogeneous memory pool includes a volatile or non-volatile memory component, a persistent memory component, and a computational component. The computational component is in communication with the persistent memory component and the volatile or non-volatile memory component. The host device is in communication with the heterogeneous memory pool, via the memory allocator, to offload computations from the host device to the heterogenous memory pool.Type: ApplicationFiled: June 14, 2022Publication date: December 14, 2023Inventors: Viacheslav Dubeyko, Jian Wang
-
Publication number: 20230376242Abstract: A system includes a first hardware architecture and computational storage. The computational storage includes a second hardware architecture, and memory storing instructions that, when executed by the second hardware architecture, causes the system to perform a first set of operations. The first set of operations include receiving instructions from the first hardware architecture, performing one or more computations on data stored in the second hardware architecture, based on the received instructions, and transmitting a result to the first hardware architecture, based on the one or more performed computations.Type: ApplicationFiled: May 17, 2022Publication date: November 23, 2023Inventors: Viacheslav Dubeyko, Jian Wang
-
Publication number: 20230359591Abstract: The present disclosure describes techniques for improving data processing. At least one transaction may be generated by a file system driver associated with a host. Each transaction comprises logical block addresses (LBAs) and information associated with at least one function. The at least one transaction may be journaled into a computational storage for offloading data processing from the host to the computational storage. The computational storage comprises a persistent memory and at least one field-programmable gate array (FPGA) core. The offloading of the data processing comprises offloading journal replay operations to the computational storage. The journal replay operations comprise applying the at least one function to at least one subset of the LBAs by the at least one FPGA core.Type: ApplicationFiled: May 6, 2022Publication date: November 9, 2023Inventors: Viacheslav Dubeyko, Jian Wang
-
Publication number: 20230359364Abstract: The present disclosure describes techniques for guaranteeing online services based on predicting failures of storage devices. Statistical data may be extracted on a regular basis by each of a plurality of storage devices. Each of the plurality of storage devices may comprise a set of NAND dies. Each of the set of NAND dies may be configured to measure and track a set of metrics indicating characteristics of each NAND die. Prediction data indicating potential failures of the plurality of storage devices may be generated. The prediction data may be shared with a host on a periodic basis. A strategy of decommissioning an aged storage device and adding a new storage device based on the prediction data may be created by the host. The data migration to the new storage device may be implemented.Type: ApplicationFiled: July 18, 2023Publication date: November 9, 2023Inventors: Viacheslav Dubeyko, Neema Mashayekhi, Cong Wang, Jian Wang
-
Patent number: 11789822Abstract: The present disclosure describes techniques for implementing fast and reliable metadata operations. A metadata area instance may be created in a persistent memory associated with a host. The metadata area instance may comprise a first portion configured to store an initial state of metadata, a second portion configured to store an actual state of the metadata, and a third portion configured to store a plurality of modifications to the metadata. A main copy of the metadata may be generated by performing write operations in the metadata area instance. The main copy of the metadata may be updated based on receiving information indicative of a modification to the metadata.Type: GrantFiled: July 22, 2022Date of Patent: October 17, 2023Assignees: LEMON INC., BEIJING YOUZHUJU NETWORK TECHNOLOGY CO. LTD.Inventors: Viacheslav Dubeyko, Jian Wang
-
Publication number: 20230325240Abstract: The present disclosure describes techniques for improved data processing. At least one management page may be generated by a host. The at least one management page comprises a plurality of management structures, and the at least one management page defines data instances, algorithms, and a computational environment. Computation may be initiated in a memory pool by performing a write operation of the at least one management page into the memory pool. The memory pool comprises a persistent memory and a plurality of field-programmable gate array (FPGA) cores. The computation in the memory pool comprises parallel data processing by at least a subset of the plurality of FPGA cores.Type: ApplicationFiled: April 7, 2022Publication date: October 12, 2023Inventors: Viacheslav Dubeyko, Jian Wang
-
Patent number: 11783176Abstract: Embodiments of storage device architecture for processing data using machine learning are disclosed. In some embodiments, the storage device includes a separate I/O core and a neural network core. The storage device can create a copy of data streams in which the data is stored, and the neural network core can process the copy of the data streams in a neural network while the I/O core can perform read or write functions on the data streams.Type: GrantFiled: March 25, 2019Date of Patent: October 10, 2023Inventors: Luiz M. Franca-Neto, Viacheslav Dubeyko
-
Patent number: 11755465Abstract: In a method for superposition of multiple commands, one or more memory pages is received. The one or more memory pages include information corresponding to one or more code lines and one or more data lines. The one or more code lines correspond to a first set of layers in a memory layer and are configured to execute one or more functions. The one or more data lines correspond to a second set of layers in the memory layer and are configured to store one or more sets of data. Each of the one or more code lines from the one or more memory pages is executed to perform one or more corresponding functions, based on the one or more data lines from the one or more memory pages. A result of each of the one or more functions is stored within the one or more data lines.Type: GrantFiled: July 29, 2022Date of Patent: September 12, 2023Assignees: Lemon Inc., Beijing Youzhuju Network Technology Co., Ltd.Inventors: Viacheslav Dubeyko, Jian Wang
-
Publication number: 20230281476Abstract: The present disclosure describes techniques for offloading knowledge base creation into a storage space. A sequence of patterns in a data stream may be identified based on a time dimension of the data stream by data processing units (DPUs) without an initiation from a Central Processing Unit (CPU). The DPUs may be associated with the storage space. The DPUs may recognize a plurality of information contexts corresponding to the sequence of patterns based on analyzing neighboring patterns of any particular pattern in the sequence of patterns. The DPUs may determine causal relations among the sequence of patterns based on detecting repetitions of any pair of information contexts among the plurality of information contexts. The causal relations may comprise a plurality of reason-consequence pairs. Knowledge of causal relationships associated with the data stream may be used to predict future states of the data stream.Type: ApplicationFiled: January 18, 2023Publication date: September 7, 2023Inventors: Viacheslav Dubeyko, Jian Wang