Abstract: Synchronizer circuits having controllable metastability are provided, one of which includes: a first flip-flop circuit comprising a first master latch connected in series with a first slave latch; and a second flip-flop circuit comprising a second master latch connected in series with a second slave latch, wherein an output of the first flip-flop circuit is connected to an input of the second flip-flop circuit, at least a portion of the first flip-flop circuit is implemented in a first PWell isolated by an underlying a deep isolation NWell, at least a portion of the first flip-flop circuit is implemented in a first NWell that electrically contacts the deep isolation NWell, the first NWell is connected to a first bias voltage that is less than a positive power supply voltage, and the first PWell is connected to a second bias voltage that is greater than a negative power supply voltage.

Abstract: An integrated circuit includes a pulse generator having at least one delay circuit with an input that receives a clock signal and an output that provides a delayed clock pulse. The delayed clock pulse has a width proportional to an amount of time required to maintain a magnitude of the clock signal. A pulse latch circuit includes a clock input coupled to receive the delayed clock pulse, a data input coupled to receive a data value, and a data output, wherein the pulse latch circuit outputs and holds the data value at the data output each time the delayed clock pulse is provided at the clock input, and the pulse latch circuit operates on a continuous voltage source that supplies power during power on and power off modes.

Abstract: Synchronizer circuits having controllable metastability are provided, one of which includes: a first flip-flop circuit comprising a first master latch connected in series with a first slave latch; and a second flip-flop circuit comprising a second master latch connected in series with a second slave latch, wherein an output of the first flip-flop circuit is connected to an input of the second flip-flop circuit, at least a portion of the first flip-flop circuit is implemented in a first PWell isolated by an underlying a deep isolation NWell, at least a portion of the first flip-flop circuit is implemented in a first NWell that electrically contacts the deep isolation NWell, the first NWell is connected to a first bias voltage that is less than a positive power supply voltage, and the first PWell is connected to a second bias voltage that is greater than a negative power supply voltage.

Abstract: Multi-bit data flip-flops are disclosed that provide bit initialization through propagation of scan bits. Input multiplexers are configured to select between input data bits and input scan bits based upon mode select signals. Master latches receive and latch outputs from the input multiplexers. Slave latches receive and latch outputs from the master latches and also provide propagated input scan bits to the input multiplexers. A first state for the mode select signals selects the input data bits for a data mode of operation, and a second state for the mode select signals selects the input scan bits for a scan mode of operation. Further, the input multiplexers, master latches, and slave latches are configured to operate in an initialization mode to pass a fixed input scan bit through the multi-bit data flip-flop based upon initialization signals (e.g., set and/or reset signals).

Abstract: Multi-bit data flip-flops are disclosed that provide bit initialization through propagation of scan bits. Input multiplexers are configured to select between input data bits and input scan bits based upon mode select signals. Master latches receive and latch outputs from the input multiplexers. Slave latches receive and latch outputs from the master latches and also provide propagated input scan bits to the input multiplexers. A first state for the mode select signals selects the input data bits for a data mode of operation, and a second state for the mode select signals selects the input scan bits for a scan mode of operation. Further, the input multiplexers, master latches, and slave latches are configured to operate in an initialization mode to pass a fixed input scan bit through the multi-bit data flip-flop based upon initialization signals (e.g., set and/or reset signals).

Abstract: A CMOS device comprises a substrate with a plurality of regions, the regions including an N-type region and a P-type region which meet each other in a PN-boundary, two or more P-type active regions embedded in the N-type region, and two or more N-type active regions embedded in the P-type region. The PN-boundary or a section of the PN-boundary is a chain of line segments. Any two adjoining line segments of the chain are angled relative to each other at their connecting point. The CMOS device can be designed using abutting standard cells. For each of two or more operating points, rise delays and fall delays associated with one or more clock cells are estimated. If the estimated rise delays and fall delays satisfy a given set of constraints, the layout of the CMOS device is accepted. Otherwise the layout is updated and a new analysis round is performed.

Abstract: A CMOS device comprises a substrate with a plurality of regions, the regions including an N-type region and a P-type region which meet each other in a PN-boundary, two or more P-type active regions embedded in the N-type region, and two or more N-type active regions embedded in the P-type region. The PN-boundary or a section of the PN-boundary is a chain of line segments. Any two adjoining line segments of the chain are angled relative to each other at their connecting point. The CMOS device can be designed using abutting standard cells. For each of two or more operating points, rise delays and fall delays associated with one or more clock cells are estimated. If the estimated rise delays and fall delays satisfy a given set of constraints, the layout of the CMOS device is accepted. Otherwise the layout is updated and a new analysis round is performed.