Abstract: A method for generating an internal clock in a radio network controller and a relevant transmission processing board. The transmission processing board comprises; a clock signal selector for extracting a clock signal from a synchronous/asynchronous line connected with a core network when said transmission processing board functions as a master transmission processing board, or for obtaining a clock signal from a clock bus of a sub-rack in which said transmission processing board is located when said transmission processing board functions as a slave transmission processing board; a phase-locked loop for generating a reference transmission clock based on the clock signal extracted or obtained by said clock signal selector; and a clock driver for transmitting the generated reference transmission clock to the clock bus of the sub-rackin which said transmission processing board is located when said transmission processing board functions as a master transmission processing board.

Abstract: The present invention provides a method for generating an internal clock in a radio network controller and a relevant transmission processing board. The transmission processing board comprises: a clock signal selector for extracting a clock signal from a synchronous/asynchronous line connected with a core network when said transmission processing board functions as a master transmission processing board, or for obtaining a clock signal from a clock bus of a sub-rack in which said transmission processing board is located when said transmission processing board functions as a slave transmission processing board; a phase-locked loop for generating a reference transmission clock based on the clock signal extracted or obtained by said clock signal selector; and a clock driver for transmitting the generated reference transmission clock to the clock bus of the sub-rack in which said transmission processing board is located when said transmission processing board functions as a master transmission processing board.

Abstract: A method of setting the polarity of a digital signal coming from a first integrated circuit, said digital signal being representative of data generated within the integrated circuit and requiring application to an input of a second integrated circuit that requires a predetermined polarity. The method comprises storing the required polarity externally to said first integrated circuit at its digital signal output, an acquisition sequence for acquiring the stored polarity while the data is inactive, and an application sequence for applying the acquired polarity to the information when active in order to generate on an output of said first integrated circuit the digital signal for application to the input of said second integrated circuit. The method is applicable in digital systems that include integrated circuits that may come from different sources.

Abstract: In a digital half-duplex frequency division multiple access radio system a mobile station is either sending or receiving. For each call between a mobile station and a base station, a first frequency is allocated for the up link direction (from the mobile station to the base station) and a second frequency is allocated for the down link direction (from the base station to the mobile station). The signals exchanged by the stations are organized in frames of predetermined fixed duration grouped into multiframes comprising a predetermined number of frames including at least one control frame. At least some of the control frames are listening frames during which the sending mobile station interrupts sending, switches to receive mode and (if appropriate) reverts to send mode.

Abstract: A programmer produces binary output signals changing state during time intervals identified by a timing signal. Each output signal goes to the active or the inactive state, i.e. starts and ends during separate time intervals. The programmer includes a memory storing a start location and an end location for each output signal, respectively, holding the signal's start and end time intervals. The operation of a read unit for reading the values in these locations is determined by a control unit using an address generator so that the possibility of a change of state is examined for each output signal during each time interval. A comparator produces an identity signal if a first field of the read location has the same value as a first field of the time interval in which the reading takes place. A decoder changes the state of the output signal corresponding to the location for which the identity signal is produced.

Abstract: A multiplexer circuit for multiplexing several clock signals is controlled by at least one selection signal, and includes for each clock signal a respective delay module producing a delayed clock signal taking the value of the clock signal in response to the appearance of a predetermined switching level of the clock signal while the selection signal is in a first state and no busy signal is then present, and interrupting the delayed clock signal in response to the appearance of the switching level if the selection signal is then in a second state. The busy signal is produced whenever any of the delay module is producing a delayed clock signal, and an output signal is derived from the delayed clock signal.