Abstract: Various implementations described herein are related to a device having a storage node with a bitcell. The device may have a first stage that performs a first write based on an internal bitline signal, a first write wordline signal and a second write wordline signal. The first stage outputs the internal bitline signal. The device may have a second stage that receives the internal bitline signal and performs a second write of the internal bitline signal to the bitcell. The device may have a third stage with write wordline ports and write bitline ports. The third stage provides the internal bitline signal based on a selected write wordline signal from a write wordline port of the write wordline ports and based on a selected bitline signal based on a write bitline port of the write bitline ports.

Abstract: Various implementations described herein are related to a device having first datapath circuitry with input devices that receive data from a number of write ports and provide first data. The device may have second datapath circuitry with logic gates that receive the first data from the input devices and provide the first data based on a read bitline signal. The device may have third datapath circuitry with output devices that receive the first data from the logic gates and provide second data to a number of read ports. Also, the number of read ports is greater than the number of write ports.

Abstract: Various implementations described herein are directed to memory circuitry having an array of bitcells and bitlines coupled to columns of the bitcells. Also, column decoder circuitry may be coupled to the bitcells via the bitlines, and the column decoder circuitry may have read logic coupled to an output node. The column decoder circuitry may have select logic coupled between a voltage supply and the read logic. Enable signals may be used to activate the select logic to pass the voltage supply to the read logic, and the bitlines provide bitline signals that activate the read logic to pass the voltage supply from the select logic to the output node.

Abstract: Various implementations described herein are directed to memory circuitry having an array of bitcells and bitlines coupled to columns of the bitcells. Also, column decoder circuitry may be coupled to the bitcells via the bitlines, and the column decoder circuitry may have read logic coupled to an output node. The column decoder circuitry may have select logic coupled between a voltage supply and the read logic. Enable signals may be used to activate the select logic to pass the voltage supply to the read logic, and the bitlines provide bitline signals that activate the read logic to pass the voltage supply from the select logic to the output node.