Patents by Inventor Viatcheslav Igor Souetinov

Viatcheslav Igor Souetinov has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6642787
    Abstract: An amplifier circuit arrangement comprises first and second long-tailed pairs of transistors each including an inductor to provide a constant current source for their respective transistor pair. Each of the transistors of the pairs is provided with a bias current on its base electrode. A differential input signal is applied between the base electrode of one transistor, via a dc blocking capacitor and an input terminal, and the base electrode of another transistor, via a dc blocking capacitor and an another input terminal. The collector electrodes of two of the transistors are connected together and to an output terminal. The collector electrodes of the other two transistors similarly are connected together and to the other output terminal. A differential output signal is provided between the output terminals. This connection of the collectors of the transistors, which can be described as parallel connection, provides summation of the differential signals provided by the transistor pairs.
    Type: Grant
    Filed: March 16, 2000
    Date of Patent: November 4, 2003
    Assignee: Mitel Semiconductor Limited
    Inventors: Viatcheslav Igor Souetinov, Peter Graham Laws
  • Publication number: 20020058492
    Abstract: An image reject mixer arrangement 1 comprises a transconductor 2, first and second mixer cores 3 and 4, first and second phase shifters 5 and 6 and a summer or combiner 7. The mixer arrangement 1 receives a single-ended RF voltage signal on a terminal 8, a differential local oscillator signal on I-LO terminals indicated at 9 and a 90° phase shifted differential local oscillator signal on Q-LO terminals 10, and provides differential IF output signals on output terminals 11. From the output of the transconductor 2 to the output of the combiner 7, the image reject mixer arrangement 1 carries signals in what can be described as a “current mode”, i.e. it is the current, not the voltage, which conveys the desired signal. In this current mode, it is advantageous to provide each active circuit block with a high output impedance and a low input impedance wherever possible.
    Type: Application
    Filed: November 4, 1998
    Publication date: May 16, 2002
    Inventors: VIATCHESLAV IGOR SOUETINOV, STEPHEN PETER GRAHAM
  • Patent number: 6324388
    Abstract: An image reject mixer for a radio receiver comprises transconductors 21 and 22, mixer stages 30 and 23 and a phase shift and combiner circuit 26. The transconductors 21 and 22 provide differential output current signals to their respective mixer stage 30 and 23. Capacitors 28 and 29 are connected between equivalent outputs of the transconductors 21 and 22 respectively. The capacitors 28 and 29 have the effect of correlating the output noise of the transconductors 21 and 22 and correlating the noise generated by the mixer stage transistors which is leaked to the inputs of the mixer stages 30 and 23, the image frequency components of which noise are thereby cancelled by the operation of the mixer stages 30 and 23 and the phase shift and combiner circuit 26. The capacitors 28 and 29 also compensate the second harmonic of the local oscillators which leak through to the inputs of the mixer stages 30 and 23. Overall, gain, noise figure and linearity can all be improved without an increase in current consumption.
    Type: Grant
    Filed: September 3, 1999
    Date of Patent: November 27, 2001
    Assignee: Mitel Semiconductor Limited
    Inventor: Viatcheslav Igor Souetinov
  • Patent number: 6147568
    Abstract: A variable attenuator comprises bipolar transistors Q1 and Q2 connected in reverse parallel between a point 1 and ground potential G. The base electrodes of the transistors Q1 and Q2 are biased independently by a control circuit 3. The collector of transistor Q1 and the emitter of transistor Q2 are commonly connected to a bias voltage provided by resistor R2 and voltage source Vr. The attenuator provides means by which the linearity, gain, power handling capabilities and noise figure of a front-end receiver can be altered. The attenuator is susceptible to integration in, for example, a radio receiver front-end.
    Type: Grant
    Filed: February 26, 1999
    Date of Patent: November 14, 2000
    Assignee: Mitel Semiconductor Limited
    Inventor: Viatcheslav Igor Souetinov