Patents by Inventor Viatcheslav Igorevich Souetinov

Viatcheslav Igorevich Souetinov has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7388446
    Abstract: A variable capacitor modulator for use in a voltage controlled oscillator, includes a differential varactor block, coupling capacitors for connecting nodes of the varactor block to a tank circuit, and an element connected between the respective nodes and ground to trim the gain of the variable capacitor modulator.
    Type: Grant
    Filed: February 10, 2005
    Date of Patent: June 17, 2008
    Assignee: Zarlink Semiconductor Ab
    Inventors: Viatcheslav Igorevich Souetinov, Alexander Alekseevich Krasin, Alexander Victorovich Koulakov
  • Patent number: 7016664
    Abstract: A mixer circuit arrangement 30 comprises a complementary transconductor circuit 31 and a mixer stage 32. The complementary transconductor circuit 31 includes two paths in parallel between a positive supply voltage VDD and ground G and is connected directly between the voltage supply terminals VDD and G. The first path includes a P-type MOS transistor TP1 and an N-type MOS transistor TN1 connected in series. Similarly, the second path includes a P-type MOS transistor TP2 and an N-type MOS transistor TN2 connected in series. The gate electrodes of the P-type transistors TP1 and TP2 are connected to a voltage bias Vbp via high value bias resistors Rb, and the gate electrodes of the N-type transistors TN1 and TN2 are connected to a second voltage bias Vbn via high value bias resistors Rb. The mixer stage 32 is connected between the output of the complementary transconductor circuit 31 and a load, the load also being connected to one of the supply terminals.
    Type: Grant
    Filed: July 3, 2002
    Date of Patent: March 21, 2006
    Assignee: Zarlink Semiconductor Limited
    Inventor: Viatcheslav Igorevich Souetinov
  • Patent number: 6683511
    Abstract: A controllable attenuator has an input and an output, and comprises a first resistive element, a first capacitor connected in series between the input and the output, a first controllable shunting transistor connected between the output and a supply terminal via a second resistive element, and a controllable bypass transistor connected between the input and the output. The controllable attenuator may form part of a radio receiver circuit, the attenuator being positioned between a matching circuit and a low-noise amplifier.
    Type: Grant
    Filed: August 28, 2002
    Date of Patent: January 27, 2004
    Assignee: Zarlink Semiconductor Limited
    Inventors: Viatcheslav Igorevich Souetinov, Serguei Vedenine
  • Publication number: 20030071697
    Abstract: A controllable attenuator has an input and an output, and comprises a first resistive element, a first capacitor connected in series between the input and the output, a first controllable shunting transistor connected between the output and a supply terminal via a second resistive element, and a controllable bypass transistor connected between the input and the output. The controllable attenuator may form part of a radio receiver circuit, the attenuator being positioned between a matching circuit and a low-noise amplifier.
    Type: Application
    Filed: August 28, 2002
    Publication date: April 17, 2003
    Applicant: Zarlink Semiconductor Limited
    Inventors: Viatcheslav Igorevich Souetinov, Serguei Vedenine
  • Publication number: 20030017816
    Abstract: A mixer circuit arrangement 30 comprises a complementary transconductor circuit 31 and a mixer stage 32. The complementary transconductor circuit 31 includes two paths in parallel between a positive supply voltage VDD and ground G and is connected directly between the voltage supply terminals VDD and G. The first path includes a P-type MOS transistor TP1 and an N-type MOS transistor TN1 connected in series. Similarly, the second path includes a P-type MOS transistor TP2 and an N-type MOS transistor TN2 connected in series. The gate electrodes of the P-type transistors TP1 and TP2 are connected to a voltage bias Vbp via high value bias resistors Rb, and the gate electrodes of the N-type transistors TN1 and TN2 are connected to a second voltage bias Vbn via high value bias resistors Rb. The mixer stage 32 is connected between the output of the complementary transconductor circuit 31 and a load, the load also being connected to one of the supply terminals.
    Type: Application
    Filed: July 3, 2002
    Publication date: January 23, 2003
    Applicant: Zarlink Semiconductor Limited
    Inventor: Viatcheslav Igorevich Souetinov