Patents by Inventor Vibhor Patale

Vibhor Patale has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11580082
    Abstract: Example object storage systems, bookkeeping engines, and methods provide quota usage monitoring for control entities, such as accounts, users, and buckets. An object data store is configured to enable control entities to access data objects associated with each control entity. Data objects are mapped to the control entities and the data objects are processed to identify object usage values corresponding to each combination of data object and control entity. Total usage values are calculated for each control entity and used to determine a data object access response for a target data object and associated control entities.
    Type: Grant
    Filed: June 14, 2019
    Date of Patent: February 14, 2023
    Assignee: Western Digital Technologies, Inc.
    Inventors: Tomy Ammuthan Cheru, Ameet Pyati, Vibhor Patale
  • Patent number: 11074002
    Abstract: Example object storage systems, meta object generators, and methods provide meta objects for replication of configuration data between data object stores. A meta object may be generated that includes configuration data. A meta object identifier may be assigned to the meta object. The meta object may be stored in a first object store with related data objects and may be replicated to a second object data store with the related data objects.
    Type: Grant
    Filed: June 20, 2019
    Date of Patent: July 27, 2021
    Assignee: Western Digital Technologies, Inc.
    Inventors: Ameet Pyati, Vibhor Patale
  • Publication number: 20200401312
    Abstract: Example object storage systems, meta object generators, and methods provide meta objects for replication of configuration data between data object stores. A meta object may be generated that includes configuration data. A meta object identifier may be assigned to the meta object. The meta object may be stored in a first object store with related data objects and may be replicated to a second object data store with the related data objects.
    Type: Application
    Filed: June 20, 2019
    Publication date: December 24, 2020
    Inventors: Ameet Pyati, Vibhor Patale
  • Publication number: 20200159706
    Abstract: Example object storage systems, bookkeeping engines, and methods provide quota usage monitoring for control entities, such as accounts, users, and buckets. An object data store is configured to enable control entities to access data objects associated with each control entity. Data objects are mapped to the control entities and the data objects are processed to identify object usage values corresponding to each combination of data object and control entity. Total usage values are calculated for each control entity and used to determine a data object access response for a target data object and associated control entities.
    Type: Application
    Filed: June 14, 2019
    Publication date: May 21, 2020
    Inventors: Tomy Ammuthan Cheru, Ameet Pyati, Vibhor Patale
  • Patent number: 9921896
    Abstract: A memory apparatus and methods are provided for preventing read errors on weak pages in a non-volatile memory system. In one example, a method includes identifying a weak page in a non-volatile memory device along a word line, wherein the weak page is partially written with at least some data; buffering data associated with the weak page to a weak page buffer that is coupled in communication with the non-volatile memory device; determining that an amount of data in the weak page buffer has reached a predetermined data level; and writing the data from the weak page buffer into the weak page along the word line in the non-volatile memory device.
    Type: Grant
    Filed: February 10, 2014
    Date of Patent: March 20, 2018
    Assignee: Virident Systems, LLC
    Inventors: Ashwin Narasimha, Vibhor Patale, Sandeep Sharma, Ajith Kumar Battaje
  • Patent number: 8392623
    Abstract: A method is described for coalescing input/output (IO) interrupts to a virtual machine (VM) running on a host computer. At a virtualization layer of the host computer that supports execution of the VM receives an IO interrupt in response to a completion of an IO request of the VM, wherein a transmission of the IO request by the VM to an IO device bypasses the virtualization layer. The virtualization layer then determines whether the VM has responded to a most recently delivered IO interrupt to the VM by the virtualization layer, and drops the IO interrupt if the VM has not responded to the most recently delivered IO interrupt, thereby failing to deliver the IO interrupt to the VM.
    Type: Grant
    Filed: May 30, 2012
    Date of Patent: March 5, 2013
    Assignee: VMware, Inc.
    Inventors: Hariharan Subramanian, Edward J. Goggin, Vibhor Patale, Rupesh Bajaj
  • Patent number: 8312175
    Abstract: A method is provided for use in a system that includes a host machine that includes multiple physical CPUs (PCPUs) and at least two cache nodes that are shared by different sets of the PCPUs, comprising: creating in a memory device multiple sets of lanes each lane set associated with a respective PCPU set; tracking levels of processing activity of the PCPUs of each PCPU set; using an MSIX vector value to associate lanes with PCPUs; receiving a IO request from any given PCPU from among the multiple PCPUs; and assigning the IO request to a respective lane based at least in part upon the PCPU set associated with the lane and PCPU processing activity levels.
    Type: Grant
    Filed: January 21, 2010
    Date of Patent: November 13, 2012
    Assignee: VMware, Inc.
    Inventors: Vibhor Patale, Rupesh Bajaj, Edward Goggin, Hariharan Subramanian
  • Patent number: 8291135
    Abstract: A system and method are provided that involve a host computing machine and an SR IOV storage adapter in which the host machine hosts a virtual machine having a guest operating system (guest) coupled for direct passthrough IOV data path and also hosts a virtualization intermediary; a guest operating system (guest) and a virtualization intermediary exchange information concerning IO completions through a shared memory space; the guest writes information to a shared memory space that is indicative of whether an IO completion queue has reached a fill level since the most recently dispatched interrupt at which it is unsafe to coalesce an interrupt; the virtualization intermediary writes information to the shared memory space that is indicative of the interrupt most recently delivered to the guest; the virtualization intermediary reads the information written by the guest to the shared memory space that is indicative of whether an IO completion queue has reached a fill level since the most recently dispatched inter
    Type: Grant
    Filed: January 15, 2010
    Date of Patent: October 16, 2012
    Assignee: VMware, Inc.
    Inventors: Hariharan Subramanian, Edward J. Goggin, Vibhor Patale, Rupesh Bajaj
  • Publication number: 20120239832
    Abstract: A method is described for coalescing input/output (IO) interrupts to a virtual machine (VM) running on a host computer. At a virtualization layer of the host computer that supports execution of the VM receives an IO interrupt in response to a completion of an IO request of the VM, wherein a transmission of the IO request by the VM to an IO device bypasses the virtualization layer. The virtualization layer then determines whether the VM has responded to a most recently delivered IO interrupt to the VM by the virtualization layer, and drops the IO interrupt if the VM has not responded to the most recently delivered IO interrupt, thereby failing to deliver the IO interrupt to the VM.
    Type: Application
    Filed: May 30, 2012
    Publication date: September 20, 2012
    Applicant: VMWARE, INC.
    Inventors: Hariharan SUBRAMANIAN, Edward J. GOGGIN, Vibhor PATALE, Rupesh BAJAJ
  • Publication number: 20110179416
    Abstract: A method is provided for use in a system that includes a host machine that includes multiple physical CPUs (PCPUs) and at least two cache nodes that are shared by different sets of the PCPUs, comprising: creating in a memory device multiple sets of lanes each lane set associated with a respective PCPU set; tracking levels of processing activity of the PCPUs of each PCPU set; using an MSIX vector value to associate lanes with PCPUs; receiving a IO request from any given PCPU from among the multiple PCPUs; and assigning the IO request to a respective lane based at least in part upon the PCPU set associated with the lane and PCPU processing activity levels.
    Type: Application
    Filed: January 21, 2010
    Publication date: July 21, 2011
    Applicant: VMWARE, INC.
    Inventors: Vibhor Patale, Rupesh Bajaj, Edward Goggin, Hariharan Subramanian
  • Publication number: 20110179413
    Abstract: A system and method are provided that involve a host computing machine and an SR IOV storage adapter in which the host machine hosts a virtual machine having a guest operating system (guest) coupled for direct passthrough IOV data path and also hosts a virtualization intermediary; a guest operating system (guest) and a virtualization intermediary exchange information concerning IO completions through a shared memory space; the guest writes information to a shared memory space that is indicative of whether an IO completion queue has reached a fill level since the most recently dispatched interrupt at which it is unsafe to coalesce an interrupt; the virtualization intermediary writes information to the shared memory space that is indicative of the interrupt most recently delivered to the guest; the virtualization intermediary reads the information written by the guest to the shared memory space that is indicative of whether an IO completion queue has reached a fill level since the most recently dispatched inter
    Type: Application
    Filed: January 15, 2010
    Publication date: July 21, 2011
    Applicant: VMWARE, INC.
    Inventors: Hariharan Subramanian, Edward J. Goggin, Vibhor Patale, Rupesh Bajaj