Patents by Inventor Vibhu Kalyan

Vibhu Kalyan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7937282
    Abstract: Generating a price schedule involves generating a graph having paths that include states with values. The graph is generated by determining the values of a successor state from the values of a predecessor state. An optimal path is selected, and a price schedule is determined from the optimal path. Computing an elasticity curve involves having a demand model, values for demand model, and filter sets that restrict the values. Elasticity curves are determined by filtering the values using filter sets, and calculating the elasticity curve using the demand model. A best-fitting elasticity curve is selected. Adjusting a demand forecast value includes estimating an inventory and a demand at a number of locations. An expected number of unrealized sales at each location is calculated. An sales forecast value is determined according to the expected number.
    Type: Grant
    Filed: May 5, 2008
    Date of Patent: May 3, 2011
    Assignee: i2 Technologies US, Inc.
    Inventors: Joachim P. Walser, Vibhu Kalyan, Srinivas Palamarthy, James M. Crawford, Jr., Mukesh Dalal
  • Publication number: 20080208678
    Abstract: Generating a price schedule involves generating a graph having paths that include states with values. The graph is generated by determining the values of a successor state from the values of a predecessor state. An optimal path is selected, and a price schedule is determined from the optimal path. Computing an elasticity curve involves having a demand model, values for demand model, and filter sets that restrict the values. Elasticity curves are determined by filtering the values using filter sets, and calculating the elasticity curve using the demand model. A best-fitting elasticity curve is selected. Adjusting a demand forecast value includes estimating an inventory and a demand at a number of locations. An expected number of unrealized sales at each location is calculated. An sales forecast value is determined according to the expected number.
    Type: Application
    Filed: May 5, 2008
    Publication date: August 28, 2008
    Inventors: Joachim P. Walser, Vibhu Kalyan, Srinivas Palamarthy, James M. Crawford, Mukesh Dalal
  • Patent number: 7343355
    Abstract: Calculating price elasticity includes accessing a number of demand models and demand data describing a number of items. The demand models are evaluated in accordance with the demand data. A demand model of the evaluated demand models is selected in response to the evaluation. A price elasticity is calculated according to the selected demand model.
    Type: Grant
    Filed: October 23, 2002
    Date of Patent: March 11, 2008
    Assignee: i2 Technologies US, Inc.
    Inventors: Boyko Ivanov, Vibhu Kalyan, Sushil Ranjan
  • Publication number: 20080040202
    Abstract: Generating a price schedule involves generating a graph having paths that include states with values. The graph is generated by determining the values of a successor state from the values of a predecessor state. An optimal path is selected, and a price schedule is determined from the optimal path. Computing an elasticity curve involves having a demand model, values for demand model, and filter sets that restrict the values. Elasticity curves are determined by filtering the values using filter sets, and calculating the elasticity curve using the demand model. A best-fitting elasticity curve is selected. Adjusting a demand forecast value includes estimating an inventory and a demand at a number of locations. An expected number of unrealized sales at each location is calculated. An sales forecast value is determined according to the expected number.
    Type: Application
    Filed: October 19, 2007
    Publication date: February 14, 2008
    Inventors: Joachim Walser, Vibhu Kalyan, Srinivas Palamarthy, James Crawford, Mukesh Dalal
  • Publication number: 20080040293
    Abstract: A method of valuing products based on demand probabilities. Products are designed by identifying product components, and combining the components in various combinations to provide standard and non-standard products. Components are valued using an algorithm that considers demand probability as well as known prices of standard products. The component values are added to determine product values and may be used to make pricing and order fulfillment decisions.
    Type: Application
    Filed: October 19, 2007
    Publication date: February 14, 2008
    Inventor: Vibhu Kalyan
  • Publication number: 20080040203
    Abstract: Calculating price elasticity includes accessing a number of demand models and demand data describing a number of items. The demand models are evaluated in accordance with the demand data. A demand model of the evaluated demand models is selected in response to the evaluation. A price elasticity is calculated according to the selected demand model.
    Type: Application
    Filed: October 22, 2007
    Publication date: February 14, 2008
    Inventors: Boyko Ivanov, Vibhu Kalyan, Sushil Ranjan
  • Publication number: 20070078790
    Abstract: A method of valuing products based on demand probabilities. Products are designed by identifying product components, and combining the components in various combinations to provide standard and non-standard products. Components are valued using an algorithm that considers demand probability as well as known prices of standard products. The component values are added to determine product values and may be used to make pricing and order fulfillment decisions.
    Type: Application
    Filed: September 20, 2006
    Publication date: April 5, 2007
    Inventor: Vibhu Kalyan
  • Publication number: 20060161504
    Abstract: Generating a price schedule involves generating a graph (50) having paths that include states (52) with values (54, 56, 58). The graph (50) is generated by determining the values (56, 58) of a successor state (52) from the values (56, 58) of a predecessor state (52). An optimal path is selected, and a price schedule is determined from the optimal path. Computing an elasticity curve involves having a demand model, values for demand model, and filter sets that restrict the values. Elasticity curves are determined by filtering the values using filter sets, and calculating the elasticity curve using the demand model. An best-fitting elasticity curve is selected. Adjusting a demand forecast value (56) includes estimating an inventory and a demand at a number of locations (24). An expected number of unrealized sales at each location (24) is calculated. An sales forecast value (56) is determined according to the expected number.
    Type: Application
    Filed: March 20, 2006
    Publication date: July 20, 2006
    Inventors: Joachim Walser, Vibhu Kalyan, Srinivas Palamarthy, James Crawford, Mukesh Dalal
  • Publication number: 20030177103
    Abstract: Calculating price elasticity includes accessing a number of demand models and demand data describing a number of items. The demand models are evaluated in accordance with the demand data. A demand model of the evaluated demand models is selected in response to the evaluation. A price elasticity is calculated according to the selected demand model.
    Type: Application
    Filed: October 23, 2002
    Publication date: September 18, 2003
    Applicant: i2 Technologies US, Inc.
    Inventors: Boyko Ivanov, Vibhu Kalyan, Sushil Ranjan
  • Patent number: 5461577
    Abstract: Random logic circuitry (210) is laid out in a logic array (212) that has a plurality of row and column locations. The logic circuitry (210) implements a plurality of dynamic logic circuits, each logic circuit having a plurality of logic gate field effect transistors (224) each formed at a selected intersection of one of the row locations and a predetermined plurality of the column locations. Elongate gate conductors (584-602) are formed at selected row locations in the logic array (212), each gate conductor provided as a gate for one or more of the logic gate transistors (224). Selected ones (e.g. 514, 544) of the transistors are merged in a row direction if the logic does not require them to be isolated from one another. A plurality of elongate second conductors (222) interconnect to selected ones of the sources or drains of the transistors (224). Non-Boolean portions of the logic circuitry are formed in an adjacent tile section (214) in the semiconductor layer separate from the logic array (212).
    Type: Grant
    Filed: March 3, 1992
    Date of Patent: October 24, 1995
    Assignee: Texas Instruments Incorporated
    Inventors: Ching-Hao Shaw, Patrick Bosshart, Douglas Matzke, Vibhu Kalyan, Theodore W. Houston
  • Patent number: 5150309
    Abstract: Random logic circuitry (210) is laid out in a logic array (212) that has a plurality of row and column locations. The logic circuitry (210) implements a plurality of dynamic logic circuits, each logic circuit having a plurality of logic gate field effect transistors (224) each formed at a selected intersection of one of the row locations and one of the column locations. Elongate gate conductors (e.g., G, H, I) are formed at selected row locations in the logic array (212), each gate conductor provided as a gate for one or more of the logic gate transistors (224). A plurality of elongate second conductors (222) connect to selected ones of the sources or drains of the transistors (224) and to non-Boolean portions of the dynamic logic circuits. The non-Boolean portions are formed in an adjacent tile section (214) in the semi-conductor layer separate from the logic array (212).
    Type: Grant
    Filed: June 29, 1990
    Date of Patent: September 22, 1992
    Assignee: Texas Instruments Incorporated
    Inventors: Ching-Hao Shaw, Patrick Bosshart, Douglas Matzke, Vibhu Kalyan, Theodore Houston
  • Patent number: 5119313
    Abstract: Random logic circuitry (210) is laid out in a logic array (212) that has a plurality of row and column locations. The logic circuitry (210) implements a plurality of dynamic logic circuits, each logic circuit having a plurality of logic gate field effect transistors (224) each formed at a selected intersection of one of the row locations and a predetermined plurality of the column locations. Elongate gate conductors (584-602) are formed at selected row locations in the logic array (212), each gate conductor provided as a gate for one or more of the logic gate transistors (224). Selected ones (e.g. 514, 544) of the transistors are merged in a row direction if the logic does not require them to be isolated from one another. A plurality of elongate second conductors (222) interconnect to selected ones of the sources or drains of the transistors (224). Non-Boolean portions of the logic circuitry are formed in an adjacent tile section (214) in the semiconductor layer separate from the logic array (212).
    Type: Grant
    Filed: June 29, 1990
    Date of Patent: June 2, 1992
    Assignee: Texas Instruments Incorporated
    Inventors: Ching-Hao Shaw, Patrick Bosshart, Douglas Matzke, Vibhu Kalyan, Theodore W. Houston
  • Patent number: 4870598
    Abstract: Random logic circuitry (210) is laid out in a logic array (212) that has a plurality of row and column locations. The logic circuitry (210) implements a plurality of dynamic logic circuits, each logic circuit having a plurality of logic gate field effect transistors (224) each formed at a selected intersection of one of the row locations and one of the column locations. Elongate gate conductors (e.g., G, H, I) are formed at selected row locations in the logic array (212), each gate conductor provided as a gate for one or more of the logic gate transistors (224). A plurality of elongate second conductors (222) connect to selected ones of the sources or drains of the transistors (224) and to non-Boolean portions of the dynamic logic circuits. The non-Boolean portions are formed in an adjacent tile section (214) in the semi-conductor layer separate from the logic array (212).
    Type: Grant
    Filed: August 4, 1987
    Date of Patent: September 26, 1989
    Assignee: Texas Instruments Incorporated
    Inventors: Ching-Hao Shaw, Patrick Bosshart, Douglas Matzke, Vibhu Kalyan, Theodore Houston