Patents by Inventor Vicente D. Alcaria

Vicente D. Alcaria has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6847115
    Abstract: A packaged semiconductor device that is fabricated with a plurality of conductive leads defined in a strip that beneficially includes a radio frequency shield box. The conductive contacts are located in a housing, beneficially by insert molding or by sandwiching between a bottom piece and a top piece. The housing can further include a cavity that receives a semiconductor device, and the radio frequency shield can receive another semiconductor device. Bonding conductors electrically connect at least one semiconductor device to another semiconductor device and/or to the conductive contacts. A conductive cover is disposed over the housing. The cavity beneficially includes a beveled wall and the conductive leads and the radio frequency shield are beneficially comprised of copper.
    Type: Grant
    Filed: September 6, 2001
    Date of Patent: January 25, 2005
    Assignee: Silicon Bandwidth Inc.
    Inventors: Stanford W. Crane, Jr., Myoung-Soo Jeon, Vicente D. Alcaria
  • Patent number: 6734546
    Abstract: A micro grid array semiconductor die package includes a housing defining a cavity for holding at least one semiconductor die, said housing including a plurality of insulative side walls, each of said side walls having a bottom surface and an interior wall including a top surface, and an end plate joined to said side walls; and a plurality of substantially straight conductive leads extending through at least one of said side walls, each of said conductive leads including an internal lead section extending into the cavity from the top surface of the interior wall and a external lead section extending externally from said at least one bottom surface of said side wall.
    Type: Grant
    Filed: February 26, 2002
    Date of Patent: May 11, 2004
    Assignee: Silicon Bandwidth, Inc.
    Inventors: Stanford W. Crane, Jr., Vicente D. Alcaria, Myoung-Soo Jeon
  • Publication number: 20040042183
    Abstract: A device package having flexible leads on a flex circuit that is insert molded into a housing. The device package includes a die attach area within the housing. The flexible leads include external ends for connecting to an external circuit and internal ends for wire bonding to a device die on the die attach area. The housing includes walls that surround the die attach area such that a device die on the die attach area can be sealed with an encapsulant. The device package is beneficially implemented in a handling frame having frame members with break tabs that are insert molded to the device package. The break tabs enable easy separation of a device package from the handling frame. The handling frames are beneficially formed into an assembly chain.
    Type: Application
    Filed: September 4, 2002
    Publication date: March 4, 2004
    Inventors: Vicente D. Alcaria, Stanford W. Crane
  • Publication number: 20030162319
    Abstract: A micro grid array semiconductor die package includes a housing defining a cavity for holding at least one semiconductor die, said housing including a plurality of insulative side walls, each of said side walls having a bottom surface and an interior wall including a top surface, and an end plate joined to said side walls; and a plurality of substantially straight conductive leads extending through at least one of said side walls, each of said conductive leads including an internal lead section extending into the cavity from the top surface of the interior wall and a external lead section extending externally from said at least one bottom surface of said side wall.
    Type: Application
    Filed: February 26, 2002
    Publication date: August 28, 2003
    Applicant: Silicon Bandwidth, Inc.
    Inventors: Stanford W. Crane, Vicente D. Alcaria, Myoung-Soo Jeon
  • Patent number: 6603193
    Abstract: A semiconductor package having a molded body and a plurality of conductive pins that extend from the bottom of the molded body. The semiconductor package further includes a RF shield around a protected cavity that holds a first integrated circuit. The molded body can further include an unprotected plastic cavity for holding a second integrated circuit. The conductive pins form bonding pads that are used to electrically interconnect the first and second semiconductor devices to the external environment. A cover, beneficially comprised of copper, is disposed over the molded body. The plastic cavity beneficially includes a beveled wall that improves the routing of electrical conductors between the first integrated circuit and the second integrated circuit.
    Type: Grant
    Filed: September 6, 2001
    Date of Patent: August 5, 2003
    Assignee: Silicon Bandwidth Inc.
    Inventors: Stanford W. Crane, Jr., Myoung-Soo Jeon, Vicente D. Alcaria
  • Publication number: 20030042582
    Abstract: A packaged semiconductor device that is fabricated with a plurality of conductive leads defined in a strip that beneficially includes a radio frequency shield box. The conductive contacts are located in a housing, beneficially by insert molding or by sandwiching between a bottom piece and a top piece. The housing can further include a cavity that receives a semiconductor device, and the radio frequency shield can receive another semiconductor device. Bonding conductors electrically connect at least one semiconductor device to another semiconductor device and/or to the conductive contacts. A conductive cover is disposed over the housing. The cavity beneficially includes a beveled wall and the conductive leads and the radio frequency shield are beneficially comprised of copper.
    Type: Application
    Filed: September 6, 2001
    Publication date: March 6, 2003
    Inventors: Stanford W. Crane, Myoung-Soo Jeon, Vicente D. Alcaria
  • Publication number: 20030042596
    Abstract: A semiconductor package having a molded body and a plurality of conductive pins that extend from the bottom of the molded body. The semiconductor package further includes a RF shield around a protected cavity that holds a first integrated circuit. The molded body can further include an unprotected plastic cavity for holding a second integrated circuit. The conductive pins form bonding pads that are used to electrically interconnect the first and second semiconductor devices to the external environment. A cover, beneficially comprised of copper, is disposed over the molded body. The plastic cavity beneficially includes a beveled wall that improves the routing of electrical conductors between the first integrated circuit and the second integrated circuit.
    Type: Application
    Filed: September 6, 2001
    Publication date: March 6, 2003
    Inventors: Stanford W. Crane, Myoung-Soo Jeon, Vicente D. Alcaria