Abstract: An address generator provided on an error control chip of an optical disk storage for addressing a plurality of working buffers accessed by a CPU, an optical disk drive (ODD), and encoder/decoder circuitry during error correction operations. The address generator comprises a loading address generator that produces an adop address signal to provide linear buffer access for the CPU and ODD when data are supplied from and to the CPU and ODD for encoding and decoding. A processing address generator produces an adex address signal that provides interleaving and random buffer access for the encoder/decoder circuitry during data encoding and decoding operations. A buffer rotation control circuit produces address and data bus control signals to provide the rotation of the buffers between the CPU, ODD, and encoder/decoder circuitry in various encoding and decoding cycles to support a pipeline error control arrangement.

Abstract: A circuit for determining locations of the errors that occur during data storage tests each possible error location using an error location polynomial. Accumulating registers of a set of multiplier accumulators are loaded with the components of the error location polynomial at the start of each 120-byte word to be tested. The output signals of the accumulating registers are transferred to an XOR checksum circuit. If the output of the XOR checksum circuit is determined to be zero, the current byte of the tested word is considered to be an error location. An external clock signal corresponding to the consecutive bytes to be tested saves the outputs of the unary multipliers for multiplying by the Galois field elements .alpha..sup.123 -.alpha..sup.131, through a feedback loop to the multiplier accumulating registers.

Abstract: For error correction circuitry capable of correcting a maximum of 8 bytes for every 120 byte code word in an optical disk storage, a shortened Reed-Solomon (120,104) code over the Galois field GF(2.sup.8) is used. Cyclic Redundancy Check (CRC) and Reed-Solomon (RS) encoders generate CRC and RS code words to be supplied to the optical disk storage. A syndrome generator receives the RS code words unloaded from the storage and detects errors in unloaded data. A CRC decoder receives the CRC code words unloaded from the storage and checks parity errors. For coding and decoding, the components of the error correction circuitry utilize unary multipliers having a plurality of XOR gates for multiplying by a Galois field element .alpha..sup.i. In order to provide fewer signal paths in the unary multipliers, the Galois field is generated using the primitive element .beta..sup.106 for poly 15, the primitive element .beta..sup.127 for poly 6 and the primitive element .beta..sup.128 for poly 5.

Abstract: In an error correction system, which incorporates Cyclic Redundancy Check (CRC) and a Reed-Solomon (RS) code, original data are encoded simultaneously by CRC and RS encoders. The CRC encoder processes the words 0-9 of the original data to form CRC check bytes, which become the last bytes in words 6, 7, 8 and 9. The RS encoder processes 104-byte words 0-9 of original data to form 16 redundant RS bytes per word. The words 0-5 are simultaneously supplied from a codeword memory to CRC and RS encoders. The redundant RS bytes generated by the RS encoder are sent back to the codeword memory, while the CRC encoder saves the CRC check bytes in local registers. For words 6-9 the RS encoder processes the bytes of original data and stops processing before the CRC bytes. It then temporarily saves the generated data in the codeword memory and waits for the CRC encoder to finish encoding. Once the CRC encoder completes, the CRC bytes corresponding to the words 6-9 are processed by the RS.