Abstract: A high-speed network switch includes a data bus for transmitting data between devices. The data bus includes a plurality of data lines and a clock line. As packet data is received by the high-speed network switch, the packet data is divided into byte-wide cells for transmission over the data lines. While the cells are transmitted over the data lines, a half-speed clock is transmitted over the clock line. Transitions in the half-speed clock occur during transmission of the cell data. The transitions are used by a receiving device to sample the byte-wide cells.

Abstract: A network switch divides incoming frame data into cells. Each of the cells include a source identification field. Depending upon bandwidth availability and upon cell priority, the cells are transmitted over a switch bus. The cells are then routed based upon the source identification field. The network switch determines bandwidth usage by monitoring the switch bus. Upon detection of a start-of-frame cell, the network switch increments a bandwidth counter. Upon detection of an end-of-frame cell, the network switch adds an entry to a decrement FIFO. After a switch bus latency period, the network switch removes the entry from the decrement FIFO and decrements the bandwidth counter.

Abstract: An apparatus for and method of assigning a VLAN tag to a frame received at a port of a switch are disclosed. The apparatus includes a content addressable memory, a data frame memory, a search circuit, and a tagging circuit. The content addressable memory stores tagging information, the tagging information including lookup data and associated tag data. The frame memory stores at least part of a data frame, the part including data frame information. The search circuit is connected to the content addressable memory and the data frame memory. The search circuit reads the data frame information, searches the content addressable memory for the lookup data corresponding to the data frame information, and reads a corresponding subset of the associated tag data. The tagging circuit is connected to the search circuit and the data frame memory. The tagging circuit writes in the data frame memory a VLAN tag including the corresponding subset of the associated tag data.