Abstract: A signal is sent into a first surface of a structure at an angle relative to the first surface of the structure using a transducer array, wherein the structure has a second surface with a portion non-parallel to the first surface. An ultrasound response signal is formed at the portion of the second surface of the structure. The ultrasound response signal is received at the transducer array.

Abstract: A signal is sent into a first surface of a structure at an angle relative to the first surface of the structure using a transducer array, wherein the structure has a second surface with a portion non-parallel to the first surface. An ultrasound response signal is formed at the portion of the second surface of the structure. The ultrasound response signal is received at the transducer array.

Abstract: A method for inspecting a composite structure includes acquiring an image of the composite structure. The composite structure includes at least a first ply and a second ply adjacent the first ply. The method also includes transforming the image into a binary image, and determining a first boundary line between the first ply and the second ply. The method further includes characterizing an irregularity in the composite structure based at least partially on the first boundary line.

Abstract: A method for monitoring and verifying a manufacturing process performed by an operator on a workpiece in a work area. The method includes positioning one or more cameras in the work area, such that the operator and the workpiece are in a field of view of each of the cameras. The method includes using a computer system configured for controlling the cameras to record and process images of the workpiece and images of operator actions relating to the manufacturing process, all recorded by the cameras during or at completion of each of a plurality of tasks in the manufacturing process to obtain recorded images. The method includes storing the recorded images, comparing the recorded images against a reference image library comprising references images corresponding to each recorded image to detect any differences between the recorded image and the respective corresponding reference image, and generating a data record.

Abstract: Power saving techniques are provided for processing circuitry on image sensors. Processing circuitry may include one or more processing blocks. The processing blocks may receive pixel data in the form of lines separated by blanking time. To reduce power consumption, each processing block may have a clock that is enabled when processing data and disabled during blanking time. The processing blocks may have respective clocks that are enabled and disabled at different times. Timing control circuitry may provide a clock enable signal to a first processing block. Each processing block may receive a clock enable signal and output a time-shifted clock enable signal for a subsequent processing block.

Abstract: Power saving techniques are provided for processing circuitry on image sensors. Processing circuitry may include one or more processing blocks. The processing blocks may receive pixel data in the form of lines separated by blanking time. To reduce power consumption, each processing block may have a clock that is enabled when processing data and disabled during blanking time. The processing blocks may have respective clocks that are enabled and disabled at different times. Timing control circuitry may provide a clock enable signal to a first processing block. Each processing block may receive a clock enable signal and output a time-shifted clock enable signal for a subsequent processing block.

Abstract: Method and system for testing an integrated circuit and more particularly, for determining timing associated with an input or output of an embedded circuit, in an integrated circuit for testing are described. A bit is adjustably delayed with a first adjustable delay to provide a delayed bit. The delayed bit is provided to a bus, such as an input bus for example, of the embedded circuit as a second vector. A third vector is output from the embedded circuit responsive to the second vector. A fourth vector is obtained having second multiple bits. The fourth vector is compared with the third vector to determine a period of delay associated with at least approximately a maximum operating frequency of the embedded circuit.

Abstract: An apparatus includes a register of an integrated circuit for shifting a scan test pattern in response to a scan enable signal. The register includes: a shift input for receiving the scan test pattern; a system logic input for receiving a system logic signal; a clock input for receiving a next clock pulse; a scan enable input for switching the register between a shift mode and a normal mode; a register output for latching the shift input in the shift mode or the system logic input in the normal mode in response to the next clock pulse; and a scan enable gating circuit coupled to the scan enable input for holding the register in the shift mode while the scan enable signal is in the shift mode and immediately following a transition of the scan enable signal from the shift mode to the normal mode until after the register output has latched the shift input in response to the next clock pulse following the transition of the scan enable signal to the normal mode.

Abstract: An apparatus includes a register of an integrated circuit for shifting a scan test pattern in response to a scan enable signal. The register includes: a shift input for receiving the scan test pattern; a system logic input for receiving a system logic signal; a clock input for receiving a next clock pulse; a scan enable input for switching the register between a shift mode and a normal mode; a register output for latching the shift input in the shift mode or the system logic input in the normal mode in response to the next clock pulse; and a scan enable gating circuit coupled to the scan enable input for holding the register in the shift mode while the scan enable signal is in the shift mode and immediately following a transition of the scan enable signal from the shift mode to the normal mode until after the register output has latched the shift input in response to the next clock pulse following the transition of the scan enable signal to the normal mode.