Abstract: A single multifunctional structure can be used to determine the alignment accuracy of the contact layer and the interconnect layer by inline visual inspection and by determination of the end of line electrical resistance properties.

Abstract: A structure and method is shown for measuring a plug and interface resistance values of an inter-layer contact structure in a semiconductor device. An inter-layer contact plug interconnects two metal layers in the semiconductor device forming a pair of plug to metal layer interfaces. A conductive trace is formed in an inter-metal dielectric layer between the metal layers, where the conductive trace couples the conductive plug to a pair of externally accessible pads. Each of the metal layers has a pair of pads. Using the pads coupled to the conductive trace, current is forced through each of the plug to metal interfaces and a voltage difference across each interface is measured in order to obtain the resistance of each interface. The total resistance of the inter-layer contact plug is similarly obtained and the resistance of the plug itself is obtained by subtracting the resistance of the two interfaces from the total resistance.

Abstract: The system and method of the present invention enable the effective and efficient determination of the misalignment between openings located in the contact layer and the interconnect layer, respectively. In this way, defective semiconductors produced in semiconductor wafer fabrication can be readily identified and segregated for shipment to customers. A single multifunctional structure formed in the contact layer can be used to determine the alignment accuracy of the contact layer and the interconnect layer by (a) inline visual inspection and (b) determination of the end of line electrical resistance properties of the semiconductor wafer. Hence the use of the multi-functional aspects of this invention eliminates the correlation issues with the structure.

Abstract: Circuitry for testing and comparing ESD protection structures is provided on a semiconductor integrated circuit. Analysis of charge transmitted to a test capacitor on board the chip provides for improved accuracy in evaluating performance of the ESD protection structure. Moreover, multiple ESD structures can be implemented and accurately compared to one another on a test chip as described. The disclosed methods and apparatus are usefull in reduced turn-around time and more accurate evaluation and comparison of ESD protection structures in integrated circuits.