Abstract: A context switching system for a multi-thread execution pipeline loop having a pipeline latency and a method of operation thereof. In one embodiment, the context switching system includes a context switch requesting subsystem configured to: (1) detect a device request from a thread executing within the multi-thread execution pipeline loop for access to a device having a fulfillment latency exceeding the pipeline latency, and (2) generate a context switch request for the thread. The context switching system further includes a context controller subsystem configured to receive the context switch request and prevent the thread from executing until the device request is fulfilled.

Abstract: A fast pattern processor having an internal function bus and an external function bus. In one embodiment, a fast pattern processor includes: (1) an internal function bus, (2) an external function bus, (3) a context memory having a block buffer and a argument signature register wherein the block buffer includes processing blocks associated with a protocol data unit (PDU), (4) a pattern processing engine, associated with the context memory, that performs pattern matching and (5) a function interface system having (5A) a controller arbitration subsystem and (5B) a dispatch subsystem.

Abstract: A virtual reassembly system for use with a fast pattern processor and a method of operating the same. In one embodiment, the virtual reassembly system includes a first pass subsystem configured to convert a packet of a protocol data unit into at least one processing block, queue the at least one processing block based upon a header of the packet and determine if the packet is a last packet of the protocol data unit. The virtual reassembly system further includes a second pass subsystem configured to virtually reassemble the protocol data unit by retrieving the at least one processing block based upon the queue.

Abstract: A method and apparatus for preventing denial of service type attacks on data networks is described. The method involves scanning the contents of the data packets flowing over the data network using a traffic flow scanning engine. The data packets are reordered and reassembled and then the payload contents are scanned to determine whether they conform to predetermined requirements. Data packets which do not reorder or reassemble correctly or which do not conform to the predetermined requirements may be dropped. Dropping packets which do not reorder or reassemble correctly or which do not conform to the predetermined requirements prevent denial of service attack which exploit bugs in the TCP/IP implementation or shortcomings in the TCP/IP specification The traffic flow scanning engine is further operable to determine whether the data packets are associated with validated traffic flows.

Abstract: A function interface system for use with a fast pattern processor having an internal function bus and an external function bus and a method of operating the same. In one embodiment, the function interface system includes a controller arbitration subsystem configured to process an issued function request received from at least one of the internal function bus and the external function bus and a dispatch subsystem configured to retrieve the issued function request and dispatch the issued function request to at least one associated co-processor via the controller arbitration subsystem.

Abstract: A virtual reassembly system for use with a fast pattern processor and a method of operating the same. In one embodiment, the virtual reassembly system includes a first pass subsystem configured to convert a packet of a protocol data unit into at least one processing block, queue the at least one processing block based upon a header of the packet and determine if the packet is a last packet of the protocol data unit. The virtual reassembly system further includes a second pass subsystem configured to virtually reassemble the protocol data unit by retrieving the at least one processing block based upon the queue.

Abstract: A database and database management system are implemented entirely in hardware. The information forming the database is stored in random access memory which is connected to a data flow engine. The data flow engine is able to process statements in standard database protocols such as SQL and XML, and to manipulate (read, write and alter) the database in accordance with the statements. The data flow engine is connected to a microprocessor that receives the statements from the database user or database application server and sends them to the data flow engine for processing. The results from the data flow engine are returned to the microprocessor and the microprocessor then returns the results to the user or application server.

Abstract: A content aware network device is described that is able to scan the contents of entire data packets including header and payload information. The network device includes a physical interface for converting analog network signal into bit streams and vise versa. The bit stream from the physical interface is sent to a traffic flow scanning processor that may be, but is not necessarily, divided into a header processor and a payload analyzer. The header processor scans the header information from each data packet, which is used to determine routing information and session identification. The payload analyzer scans the data packet's payload and matches the payload against a database of known strings. The payload analyzer is able to scan across packet boundaries and to scan for strings of variable and arbitrary length. Once the payload has been scanned the network device can operate on the data packet based on the results of the payload analyzer.

Abstract: A context switching system for a multi-thread execution pipeline loop having a pipeline latency and a method of operation thereof. In one embodiment, the context switching system includes a context switch requesting subsystem configured to: (1) detect a device request from a thread executing within the multi-thread execution pipeline loop for access to a device having a fulfillment latency exceeding the pipeline latency, and (2) generate a context switch request for the thread. The context switching system further includes a context controller subsystem configured to receive the context switch request and prevent the thread from executing until the device request is fulfilled.

Abstract: A function interface system for use with a fast pattern processor having an internal function bus and an external function bus and a method of operating the same. In one embodiment, the function interface system includes a controller arbitration subsystem configured to process an issued function request received from at least one of the internal function bus and the external function bus and a dispatch subsystem configured to retrieve the issued function request and dispatch the issued function request to at least one associated co-processor via the controller arbitration subsystem.

Abstract: A virtual reassembly system for use with a fast pattern processor and a method of operating the same. In one embodiment, the virtual reassembly system includes a first pass subsystem configured to convert a packet of a protocol data unit into at least one processing block, queue the at least one processing block based upon a header of the packet and determine if the packet is a last packet of the protocol data unit. The virtual reassembly system further includes a second pass subsystem configured to virtually reassemble the protocol data unit by retrieving the at least one processing block based upon the queue.

Abstract: A method and apparatus is provided for searching a knowledge base to determine whether a search object matches any of a plurality of knowledge base entries. Initially, at least one search object bit is selected and examined to determine whether the knowledge base includes a partially matched entry that represents the same bit pattern in its corresponding bits, and when it does not, the search is terminated indicating no match. When the knowledge base does include a partially matched entry, the group of partially matched entries is identified. Thereafter, at least one previously unselected search object bit is selected and examined to determine whether the group of partially matched entries includes a further matched entry that represents the same bit pattern in its bits that correspond to the previously unselected search object bit and when it does not, the search is terminated indicating no match.

Abstract: A method and apparatus is provided for searching a knowledge base to determine whether a search object matches any of a plurality of knowledge base entries. Initially, at least one search object bit is selected and examined to determine whether the knowledge base includes a partially matched entry that represents the same bit pattern in its corresponding bits, and when it does not, the search is terminated indicating no match. When the knowledge base does include a partially matched entry, the group of partially matched entries is identified. Thereafter, at least one previously unselected search object bit is selected and examined to determine whether the group of partially matched entries includes a further matched entry that represents the same bit pattern in its bits that correspond to the previously unselected search object bit and when it does not, the search is terminated indicating no match.

Abstract: An industrial process control system to be used with processes which are geographically spread out over a relatively wide field area, with portions thereof located in respective zones, and wherein the process has associated therewith a large number of instrumentation elements including sensing elements and operating elements for controlling actuators such as process valves. The control system includes a central station with a digital computer which directs signals to a number of primary transmitter/receiver units each producing a swept-carrier wireless signal for transmission to a respective one of the field area zones. Within each zone are a plurality of local transmitter/receiver units similar to the primary units, with each local unit being assigned to one or more sensing elements and/or one or more operating elements.

Abstract: A receiver for a carrier that is swept in frequency in a predetermined manner over a bandwidth comprises frequency tracking with continuous self-synchronization. The frequency tracking permits the carrier to be filtered by a narrowband filter. The filtered carrier is then fed to a frequency discriminator to produce an error signal. A highly-selective phase-locked loop synchronizes only to the desired component of the error signal in frequency and in phase. The output of the phase-locked loop, after appropriate shaping, is the control signal for tracking synchronously the incoming wave. The output data are obtained at detection after the narrowband filtering.