Abstract: A computing device for use in decision tree computation is provided. The computing device may include a software program executed by a processor using portions of memory of the computing device, the software program being configured to receive user input from a user input device associated with the computing device, and in response, to perform a decision tree task. The computing device may further include a decision tree computation device implemented in hardware as a logic circuit distinct from the processor, and which is linked to the processor by a communications interface. The decision tree computation device may be configured to receive an instruction to perform a decision tree computation associated with the decision tree task from the software program, process the instruction, and return a result to the software program via the communication interface.

Abstract: A computing device for use in decision tree computation is provided. The computing device may include a software program executed by a processor using portions of memory of the computing device, the software program being configured to receive user input from a user input device associated with the computing device, and in response, to perform a decision tree task. The computing device may further include a decision tree computation device implemented in hardware as a logic circuit distinct from the processor, and which is linked to the processor by a communications interface. The decision tree computation device may be configured to receive an instruction to perform a decision tree computation associated with the decision tree task from the software program, process the instruction, and return a result to the software program via the communication interface.

Abstract: A processing apparatus for processing multiple video programs from one or more transport streams. The processing apparatus has a transport processing circuit that includes multiple transport processor units. The transport processor units utilize a common transport processor memory unit having demux context entries containing processing and hardware state information for packet types. Each transport processor unit includes a transport interface for identifying data packets to be acquired from the transport stream, a demultiplexing processor for processing the acquired data packets, and a demultiplexing DMA unit for memory handling operations of the processed data packets. Index chaining allows the transport processor units to access information from the transport processor memory unit. The method uses indices to access demux context entries from the transport processor memory unit. Related DMA indices are used to access memory handling information from the transport processor memory unit.

Abstract: A processing apparatus for processing multiple video programs from one or more transport streams. The processing apparatus has a transport processing circuit that includes multiple transport processor units. The transport processor units utilize a common transport processor memory unit having demux context entries containing processing and hardware state information for packet types. Each transport processor unit includes a transport interface for identifying data packets to be acquired from the transport stream, a demultiplexing processor for processing the acquired data packets, and a demultiplexing DMA unit for memory handling operations ofthe processed data packets. Index chaining allows the transport processor units to access information from the transport processor memory unit. The method uses indices to access demux context entries from the transport processor memory unit. Related DMA indices are used to access memory handling information from the transport processor memory unit.

Abstract: A system and method of selecting a level of detail in a texture-mapping system. Pixels are processed in a zig-zag traversal pattern to allow determination of vertical and horizontal change values in texture map coordinates. In this manner, accurate level of detail selection is achieved without unduly reducing efficiency or throughput of the graphics system.