Abstract: Doping of the P type base region in a MOSFET or an IGBT with a combination of boron and one or more of indium, aluminum and gallium, provides a structure having a lower P type doping level in the channel portion of the structure than in the remainder of the structure without requiring counter doping of the channel. The doping level of the emitter region of an MCT is kept high everywhere except in the channel in order to provide a fast turn-off time for the MCT.

Abstract: A method of fabricating a MOS controlled thyristor (MCT) semiconductor power device which reduces process time, reduces cell size, and increases the density of turn-off channels. The method uses a single, dopant-opaque mask to form MCT structure above the bottom N and P layers, including the upper portions of PNP and NPN transistors which form the MCT and On-FETs and Off-FETs which operate the MCT. The single mask may also be used to fabricate floating field rings for the device. The method may also be used on both sides of the device to provide a Fast Turn Off (FTO) device with both On- and Off-FETs on one side and at least an Off-FET on the other side.

Abstract: One embodiment of a metal oxide semiconductor controlled thyristor in accordance with the present invention has a semiconductor wafer with opposing first and second surfaces. The wafer includes first through sixth sequential regions which are disposed one above the other. The first region includes the second surface of the wafer and each of the second through sixth regions has at least a portion which extends up to the first surface. The first, third, and sixth regions have a first type of conductivity and the second, fourth, and fifth regions have a second type of conductivity. A trench with a bottom and sidewalls extends from the first surface and passes through the fourth, fifth, and sixth regions and into the third region. A dielectric material coats the bottom and sidewalls of the trench and a conductive material fills the remainder of the trench.

Abstract: A four-region semiconductor device (that is, a p-n-p-n or n-p-n-p device) including at least one further region utilizes integral FET structure for diverting carriers away from an interior region of the device and shunting them to a main current-carrying electrode of the device, whereby the device is provided with a turn-off capability. The device requires only a small amount of energy for its turn-off control gate, and utilizes a high percentage of its semiconductor body for carrying current through the device. High speed turn-off is achieved in a particular embodiment of the device.

Abstract: A method of processing wafers for power devices in which the wafer has a desired thickness less than the thickness necessary to provide mechanical support. A silicon wafer of the desired thickness is bonded to a carrier wafer until most, if not all, of the processing steps are completed, after which the silicon wafer is separated from its carrier wafer. The carrier wafer may serve as a diffusion source, and the areas of the bonding of the silicon wafer to the carrier wafer may be selected consistent with the devices or groups of devices to be formed by the separation of the two wafers. The carrier wafer may by bonded to the device wafer over nearly the full surface area and the carrier wafer remain a part of the final device.