Patents by Inventor Victor Batinovich

Victor Batinovich has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7104804
    Abstract: An IC package for mounting to a surface of a device board includes a first IC having a first surface supporting a first plurality of conductive leads extending orthogonally from the first surface, a second IC having a second surface supporting a second plurality of conductive leads extending orthogonally from the second surface, the first and second ICs spaced apart in parallel with the first and second surfaces facing, and an interposer trace board parallel to the first and second ICs and positioned between the first and second ICs, the trace board having conducting metal traces on a non-conductive sheet material, the traces accessible from both sides of the trace board, being exposed at selected regions through the non-conductive sheet. The package is characterized in that the conductive traces contact individual ones of the first and second pluralities of conductive leads, providing conductive signal paths from the first and second ICs between the ICs and leading to edges of the IC package.
    Type: Grant
    Filed: July 25, 2001
    Date of Patent: September 12, 2006
    Assignee: Advanced Interconnect Solutions
    Inventor: Victor Batinovich
  • Publication number: 20040040855
    Abstract: A method for redistributing bond pad locations on an IC die incorporates steps of (a) depositing a dielectric layer over the IC die and opening vias through the dielectric layer to the bond pads; (b) depositing a thin seed layer of electrically conductive material over the dielectric layer and exposed bond pads, and patterning the seed layer to provide redistribution lines from individual ones of the bond pads to new locations for the bond pads; and (c) increasing the thickness of the redistribution lines by electroplating a conductive material onto the seed layer material. In some cases multiple relocations are made in the distribution.
    Type: Application
    Filed: August 28, 2002
    Publication date: March 4, 2004
    Inventor: Victor Batinovich
  • Publication number: 20020061665
    Abstract: A method for forming an extended solder column on a contact pad of an electronic device comprises steps of (a) applying a solder seed to the contact pad; (b) contacting the seed with a surface substantially parallel to and opposite the contact pad, with the seed between the surface and the pad; (c) melting the seed to wet the contact pad and the surface; (d) extending the relative separation of the surface and the contact pad, drawing the molten seed into a column; and (e) solidifying the resultant column. Further in the invention an integrated circuit (IC) assembly for mounting to a surface of a device board comprises a plurality of planar ICs interspersed with individual interposers or a or continuous interposer and conductive bars for constraining the stack and providing conductive paths to the device board.
    Type: Application
    Filed: January 14, 2002
    Publication date: May 23, 2002
    Inventor: Victor Batinovich
  • Publication number: 20020015340
    Abstract: An IC package for mounting to a surface of a device board includes a first IC having a first surface supporting a first plurality of conductive leads extending orthogonally from the first surface, a second IC having a second surface supporting a second plurality of conductive leads extending orthogonally from the second surface, the first and second ICs spaced apart in parallel with the first and second surfaces facing, and an interposer trace board parallel to the first and second ICs and positioned between the first and second ICs, the trace board having conducting metal traces on a non-conductive sheet material, the traces accessible from both sides of the trace board, being exposed at selected regions through the non-conductive sheet. The package is characterized in that the conductive traces contact individual ones of the first and second pluralities of conductive leads, providing conductive signal paths from the first and second ICs between the ICs and leading to edges of the IC package.
    Type: Application
    Filed: July 25, 2001
    Publication date: February 7, 2002
    Inventor: Victor Batinovich
  • Patent number: 5491110
    Abstract: An improved metal semiconductor package is described. The semiconductor package includes a lead frame with a top side and a bottom side. A semiconductor is positioned on the top side of the lead frame. Bond wires electrically couple the lead frame to the semiconductor die. A metallic base is positioned at the bottom side of the lead frame. A metallic cap is positioned over the top side of the lead frame. The metallic cap includes a central aperture that is aligned with the semiconductor die. An external plastic seal is used to join the metallic base, lead frame, and metallic cap. The external plastic seal may be in the form of a perimeter seal or a body seal.
    Type: Grant
    Filed: February 3, 1995
    Date of Patent: February 13, 1996
    Assignee: Integrated Packaging Assembly Corporation
    Inventors: Gerald K. Fehr, Victor Batinovich
  • Patent number: 5436407
    Abstract: An improved metal semiconductor package is described. The semiconductor package includes a lead frame with a top side and a bottom side. A semiconductor is positioned on the top side of the lead frame. Bond wires electrically couple the lead frame to the semiconductor die. A metallic base is positioned at the bottom side of the lead frame. A metallic cap is positioned over the top side of the lead frame. The metallic cap includes a central aperture that is aligned with the semiconductor die. An external plastic seal is used to join the metallic base, lead frame, and metallic cap. The external plastic seal may be in the form of a perimeter seal or a body seal.
    Type: Grant
    Filed: June 13, 1994
    Date of Patent: July 25, 1995
    Assignee: Integrated Packaging Assembly Corporation
    Inventors: Gerald K. Fehr, Victor Batinovich
  • Patent number: 4451972
    Abstract: Electronic chip having a composite stratified metal back and method of making it in which strata of metal and/or metal alloys are deposited on the back of the silicon base or a wafer carrying a plurality of circuit components on its face at least one of the strata being resistant to passage of copper at attaching and operational temperatures, and a stratum of solder is provided on the surface of the previously deposited strata for joining the chip to a lead frame.
    Type: Grant
    Filed: April 12, 1982
    Date of Patent: June 5, 1984
    Assignee: National Semiconductor Corporation
    Inventor: Victor A. Batinovich
  • Patent number: 4320865
    Abstract: A system for automatic and high production attachment of dies to heat sinks and other supporting structure includes an open ended gas tunnel having an inlet at one end, an outlet at the other end with means for indexing supporting structures step by step through the tunnel with heating means for heating the supporting structure in a first portion of the tunnel with automatic manipulating means for selecting and introducing first, a solder pre-form onto the heated support structure and then a die onto the melted solder with a source of forming gas continuously fed into the tunnel for controlling the atmosphere therein, and also for quickly quenching and cooling the solder after the die has been placed thereon.
    Type: Grant
    Filed: March 21, 1980
    Date of Patent: March 23, 1982
    Assignee: National Semiconductor Corporation
    Inventor: Victor A. Batinovich