Abstract: A fast pattern processor having an internal function bus and an external function bus. In one embodiment, a fast pattern processor includes: (1) an internal function bus, (2) an external function bus, (3) a context memory having a block buffer and a argument signature register wherein the block buffer includes processing blocks associated with a protocol data unit (PDU), (4) a pattern processing engine, associated with the context memory, that performs pattern matching and (5) a function interface system having (5A) a controller arbitration subsystem and (5B) a dispatch subsystem.

Abstract: A traffic prediction component may automatically generate predicted traffic profiles for web sites based on tags that characterize the sites. An initial set of tags can be selected for a web site based on a set of predefined rules. An initial traffic profile may be selected based on the initial set of tags. The predicted profile of user traffic is then generated based on the initial set of tags and on the initial traffic profile.

Abstract: A virtual reassembly system for use with a fast pattern processor and a method of operating the same. In one embodiment, the virtual reassembly system includes a first pass subsystem configured to convert a packet of a protocol data unit into at least one processing block, queue the at least one processing block based upon a header of the packet and determine if the packet is a last packet of the protocol data unit. The virtual reassembly system further includes a second pass subsystem configured to virtually reassemble the protocol data unit by retrieving the at least one processing block based upon the queue.

Abstract: A method and apparatus for preventing denial of service type attacks on data networks is described. The method involves scanning the contents of the data packets flowing over the data network using a traffic flow scanning engine. The data packets are reordered and reassembled and then the payload contents are scanned to determine whether they conform to predetermined requirements. Data packets which do not reorder or reassemble correctly or which do not conform to the predetermined requirements may be dropped. Dropping packets which do not reorder or reassemble correctly or which do not conform to the predetermined requirements prevent denial of service attack which exploit bugs in the TCP/IP implementation or shortcomings in the TCP/IP specification The traffic flow scanning engine is further operable to determine whether the data packets are associated with validated traffic flows.

Abstract: A function interface system for use with a fast pattern processor having an internal function bus and an external function bus and a method of operating the same. In one embodiment, the function interface system includes a controller arbitration subsystem configured to process an issued function request received from at least one of the internal function bus and the external function bus and a dispatch subsystem configured to retrieve the issued function request and dispatch the issued function request to at least one associated co-processor via the controller arbitration subsystem.

Abstract: A fast pattern processor having an internal function bus and an external function bus. In one embodiment, a fast pattern processor includes: (1) an internal function bus, (2) an external function bus, (3) a context memory having a block buffer and a argument signature register wherein the block buffer includes processing blocks associated with a protocol data unit (PDU), (4) a pattern processing engine, associated with the context memory, that performs pattern matching and (5) a function interface system having (5A) a controller arbitration subsystem and (5B) a dispatch subsystem.

Abstract: A data structure for a hardware database system is described. The data structure is made up of multiple sub-trees interconnected to form a graph structure. Each sub-tree begins at a memory location, or root address. Next the sub-tree includes profile information relevant to the sub-tree, such profile information can include, but is not limited to, information on the type of data being stored, the number of entries in the sub-tree, privilege information for accessing the sub-tree, etc. After the profile information the sub-trees contain search strings, or differential bits that lead to each of the entries in the sub-tree. Each search string ends in a result string. The result string can be actual data, can be a pointer to another sub-tree, can be a function call, or can be any other useful data or entry.

Abstract: A graph processor for a hardware database is described which is operable to manipulate, such as reading, writing, or altering, information in a database, or other collection of information. The graph processor includes a read engine and a write engine, the read engine operable to compare the search object against the information in the database and return results based on the comparison. The write engine is operable to write new information into the database by first locating the first differential bit between the information to be written and the existing contents of the database. Once the differential bit has been located the write engine creates a new branch and inserts the data into the database.

Abstract: A method for implementing a hardware database management system in hardware is described. A parser takes standardized database statements and converts those statements into a set of executable instructions and associated data objects. The executable instructions and data objects are then sent to the execution tree engine where an execution tree is created, the execution tree forming the order of execution for the executable instructions. The graph engine receives those executable instructions from the execution tree engine that require access to the database in memory and manipulates the information in the database as required by the executable instructions for implementing the standardized database statement.

Abstract: A virtual reassembly system for use with a fast pattern processor and a method of operating the same. In one embodiment, the virtual reassembly system includes a first pass subsystem configured to convert a packet of a protocol data unit into at least one processing block, queue the at least one processing block based upon a header of the packet and determine if the packet is a last packet of the protocol data unit. The virtual reassembly system further includes a second pass subsystem configured to virtually reassemble the protocol data unit by retrieving the at least one processing block based upon the queue.

Abstract: An architecture for a hardware database management system is described. A data flow engine is connected to memory storing the information making up a database or databases. The data flow engine is formed by a parser, an execution tree engine and a graph engine. The parser takes standardized database statements and converts those statements into a set of executable instructions and associated data objects. The executable instructions and data objects are then sent to the execution tree engine where an execution tree is created, the execution tree forming the order of execution for the executable instructions. The graph engine receives those executable instructions from the execution tree engine that require access to the database in memory and manipulates the information in the database as required by the executable instructions for implementing the standardized database statement.

Abstract: A virtual reassembly system for use with a fast pattern processor and a method of operating the same. In one embodiment, the virtual reassembly system includes a first pass subsystem configured to convert a packet of a protocol data unit into at least one processing block, queue the at least one processing block based upon a header of the packet and determine if the packet is a last packet of the protocol data unit. The virtual reassembly system further includes a second pass subsystem configured to virtually reassemble the protocol data unit by retrieving the at least one processing block based upon the queue.

Abstract: A database and database management system are implemented entirely in hardware. The information forming the database is stored in random access memory which is connected to a data flow engine. The data flow engine is able to process statements in standard database protocols such as SQL and XML, and to manipulate (read, write and alter) the database in accordance with the statements. The data flow engine is connected to a microprocessor that receives the statements from the database user or database application server and sends them to the data flow engine for processing. The results from the data flow engine are returned to the microprocessor and the microprocessor then returns the results to the user or application server.

Abstract: A content aware network device is described that is able to scan the contents of entire data packets including header and payload information. The network device includes a physical interface for converting analog network signal into bit streams and vise versa. The bit stream from the physical interface is sent to a traffic flow scanning processor that may be, but is not necessarily, divided into a header processor and a payload analyzer. The header processor scans the header information from each data packet, which is used to determine routing information and session identification. The payload analyzer scans the data packet's payload and matches the payload against a database of known strings. The payload analyzer is able to scan across packet boundaries and to scan for strings of variable and arbitrary length. Once the payload has been scanned the network device can operate on the data packet based on the results of the payload analyzer.

Abstract: A context switching system for a multi-thread execution pipeline loop having a pipeline latency and a method of operation thereof. In one embodiment, the context switching system includes a context switch requesting subsystem configured to: (1) detect a device request from a thread executing within the multi-thread execution pipeline loop for access to a device having a fulfillment latency exceeding the pipeline latency, and (2) generate a context switch request for the thread. The context switching system further includes a context controller subsystem configured to receive the context switch request and prevent the thread from executing until the device request is fulfilled.

Abstract: A function interface system for use with a fast pattern processor having an internal function bus and an external function bus and a method of operating the same. In one embodiment, the function interface system includes a controller arbitration subsystem configured to process an issued function request received from at least one of the internal function bus and the external function bus and a dispatch subsystem configured to retrieve the issued function request and dispatch the issued function request to at least one associated co-processor via the controller arbitration subsystem.

Abstract: A virtual reassembly system for use with a fast pattern processor and a method of operating the same. In one embodiment, the virtual reassembly system includes a first pass subsystem configured to convert a packet of a protocol data unit into at least one processing block, queue the at least one processing block based upon a header of the packet and determine if the packet is a last packet of the protocol data unit. The virtual reassembly system further includes a second pass subsystem configured to virtually reassemble the protocol data unit by retrieving the at least one processing block based upon the queue.

Abstract: A method and apparatus is provided for searching a knowledge base to determine whether a search object matches any of a plurality of knowledge base entries. Initially, at least one search object bit is selected and examined to determine whether the knowledge base includes a partially matched entry that represents the same bit pattern in its corresponding bits, and when it does not, the search is terminated indicating no match. When the knowledge base does include a partially matched entry, the group of partially matched entries is identified. Thereafter, at least one previously unselected search object bit is selected and examined to determine whether the group of partially matched entries includes a further matched entry that represents the same bit pattern in its bits that correspond to the previously unselected search object bit and when it does not, the search is terminated indicating no match.

Abstract: A method and apparatus is provided for searching a knowledge base to determine whether a search object matches any of a plurality of knowledge base entries. Initially, at least one search object bit is selected and examined to determine whether the knowledge base includes a partially matched entry that represents the same bit pattern in its corresponding bits, and when it does not, the search is terminated indicating no match. When the knowledge base does include a partially matched entry, the group of partially matched entries is identified. Thereafter, at least one previously unselected search object bit is selected and examined to determine whether the group of partially matched entries includes a further matched entry that represents the same bit pattern in its bits that correspond to the previously unselected search object bit and when it does not, the search is terminated indicating no match.

Abstract: An internetworking system for exchanging packets of information between networks, the system comprising a network interface module for connecting a network to the system, receiving packets from the network in a native packet format used by the network and converting each received native packet to a packet having a generic format common to all networks connected to the system, and converting each of the generic packets to the native packet format for transmission to the network; a communication channel for carrying the generic packets to and from the network interface module, the channel having bandwidth; a first processing module for controlling dynamic allocation and deallocation of the channel bandwidth to the network connected to the system via the network interface module; and a second processing module for receiving all of the generic packets put on the channel by the network interface module, determining a destination network interface module for each of the generic packets on the channel, determining w