Patents by Inventor Victor C. Liang

Victor C. Liang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method for making reliable interconnect structures
    Patent number: 6093658
    Abstract: Disclosed is a method for making reliable interconnect structures on a semiconductor wafer having a first dielectric layer. The method includes plasma patterning a first metallization layer over the first dielectric layer. Forming a second dielectric layer over the first metallization layer and the first dielectric layer. Forming a plurality of tungsten plugs in the second dielectric layer, such that each of the plurality of tungsten plugs are in electrical contact with the first metallization layer. Plasma patterning a second metallization layer over the second dielectric layer and the plurality of tungsten plugs, such that at least a gap over at least one of the tungsten plugs is not covered by the second metallization layer and a positive charge is built-up on at least part of the second metallization layer.
    Type: Grant
    Filed: December 22, 1997
    Date of Patent: July 25, 2000
    Assignee: Philips Electronics North America Corporation
    Inventors: Subhas Bothra, Harlan Lee Sur, Jr., Victor C. Liang
  • Method and apparatus for rapidly discharging plasma etched interconnect structures
    Patent number: 6077762
    Abstract: Disclosed is a method for making reliable interconnect structures on a semiconductor substrate having a first dielectric layer. The method includes plasma patterning a first metallization layer that lies over the first dielectric layer. Forming a second dielectric layer over the first metallization layer and the first dielectric layer. Forming a plurality of tungsten plugs in the second dielectric layer, such that each of the plurality of tungsten plugs are in electrical contact with the first metallization layer. Plasma patterning a second metallization layer over the second dielectric layer and the plurality of tungsten plugs, such that at least a gap over at least one of the tungsten plugs is not covered by the second metallization layer and a positive charge is built-up on at least part of the second metallization layer. The method further includes contacting the second metallization layer with a conductive liquid that is electrically grounded.
    Type: Grant
    Filed: December 22, 1997
    Date of Patent: June 20, 2000
    Assignee: VLSI Technology, Inc.
    Inventors: Victor C. Liang, Subhas Bothra, Harlan Lee Sur, Jr.