Patents by Inventor Victor-Chiang Liang
Victor-Chiang Liang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11936299Abstract: A transistor includes a gate structure over a substrate, wherein the substrate includes a channel region. The transistor further includes a source/drain (S/D) in the substrate adjacent to the gate structure. The transistor further includes a lightly doped drain (LDD) region adjacent to the S/D, wherein a dopant concentration in the first LDD is less than a dopant concentration in the S/D. The transistor further includes a doping extension region adjacent the LDD region, wherein the doping extension region extends farther under the gate structure than the LDD region, and a maximum depth of the doping extension region is 10-times to 30-times greater than a maximum depth of the LDD.Type: GrantFiled: September 21, 2020Date of Patent: March 19, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chu Fu Chen, Chi-Feng Huang, Chia-Chung Chen, Chin-Lung Chen, Victor Chiang Liang, Chia-Cheng Pao
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Publication number: 20240088224Abstract: A semiconductor structure includes a first gate structure, a second gate structure coupled to the first gate structure, a source region, a first drain region, and a second drain region. The source region is surrounded by the first gate structure and the second gate structure. The first drain region is separated from the source region by the first gate structure. The second drain region is separated from the source region by the second gat structure. A shape of the first drain region and a shape of the second drain region are different from each other from a plan view.Type: ApplicationFiled: November 14, 2023Publication date: March 14, 2024Inventors: HSING-I TSAI, FU-HUAN TSAI, CHIA-CHUNG CHEN, HSIAO-CHUN LEE, CHI-FENG HUANG, CHO-YING LU, VICTOR CHIANG LIANG
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Patent number: 11908884Abstract: An inductive device includes an insulating layer, a lower magnetic layer, and an upper magnetic layer that are formed such that the insulating layer does not separate the lower magnetic layer and the upper magnetic layer at the outer edges or wings of the inductive device. The lower magnetic layer and the upper magnetic layer form a continuous magnetic layer around the insulating layer and the conductors of the inductive device. Magnetic leakage paths are provided by forming openings through the upper magnetic layer. The openings may be formed through the upper magnetic layer by semiconductor processes that have relatively higher precision and accuracy compared to semiconductor processes for forming the insulating layer such as spin coating. This reduces magnetic leakage path variation within the inductive device and from inductive device to inductive device.Type: GrantFiled: April 7, 2022Date of Patent: February 20, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Wei-Yu Chou, Yang-Che Chen, Chen-Hua Lin, Victor Chiang Liang, Huang-Wen Tseng, Chwen-Ming Liu
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Publication number: 20240047310Abstract: A semiconductor structure includes a molding compound having a first surface and a second surface opposite to the first surface, a passive device component disposed in the molding compound, a via penetrating the molding compound from the first surface to the second surface, a first connection structure disposed over the first surface of the molding compound and electrically coupled to the passive device component, and a second connection structure disposed over the second surface of the molding compound. The first connection structure and the second connection structure are electrically coupled to each other by the via.Type: ApplicationFiled: October 23, 2023Publication date: February 8, 2024Inventors: YANG-CHE CHEN, CHEN-HUA LIN, HUANG-WEN TSENG, VICTOR CHIANG LIANG, CHWEN-MING LIU
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Patent number: 11862467Abstract: A method of manufacturing a semiconductor structure, comprising providing a substrate; forming a fin structure over the substrate; depositing an insulation material over the fin structure; performing a plurality of ion implantation cycles in-situ with implantation energy increased or decreased stepwise; and removing at least a portion of the insulation material to expose a portion of the fin structure.Type: GrantFiled: June 14, 2022Date of Patent: January 2, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Chia-Chung Chen, Chung-Hao Chu, Chi-Feng Huang, Victor Chiang Liang
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Patent number: 11855145Abstract: A semiconductor structure includes a gate structure, a source region, a drain region, and an isolation structure. The gate structure includes a first portion, a second portion and a third portion. The first portion extends in a first direction, and the second portion and the third portion extend in a second direction. The second portion and the third portion are disposed at opposite ends of the first portion. The source region and the drain region are separated by the gate structure. The isolation structure surrounds the gate structure, the source region and the drain region. The first portion has a first sidewall, the second portion has a second sidewall, and the third portion has a third sidewall. The first sidewall, the second sidewall and the third sidewall are parallel to the first direction and aligned with each other to form a straight line.Type: GrantFiled: August 31, 2021Date of Patent: December 26, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Hsing-I Tsai, Fu-Huan Tsai, Chia-Chung Chen, Hsiao-Chun Lee, Chi-Feng Huang, Cho-Ying Lu, Victor Chiang Liang
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Patent number: 11854913Abstract: A method for detecting defects in a semiconductor device including singulating a die having a substrate including a circuit region and an outer border, a plurality of detecting devices disposed over the substrate and located between the circuit region and the outer border, a first probe pad and a second probe pad electrically connected to two ends of each detecting device, and a seal ring located between the outer border of the die and the detecting devices. The method further includes probing the first probe pad and the second probe pad to determine a connection status of the detecting device, and recognizing a defect when the connection status of the detecting device indicates an open circuit.Type: GrantFiled: August 9, 2021Date of Patent: December 26, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Yang-Che Chen, Wei-Yu Chou, Hong-Seng Shue, Chen-Hua Lin, Huang-Wen Tseng, Victor Chiang Liang, Chwen-Ming Liu
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Patent number: 11837526Abstract: A semiconductor structure includes a molding compound having a first surface and a second surface opposite to the first surface, a passive device component disposed in the molding compound, a via penetrating the molding compound from the first surface to the second surface, a first connection structure disposed over the first surface of the molding compound and electrically coupled to the passive device component, and a second connection structure disposed over the second surface of the molding compound. The first connection structure and the second connection structure are electrically coupled to each other by the via.Type: GrantFiled: June 24, 2019Date of Patent: December 5, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Yang-Che Chen, Chen-Hua Lin, Huang-Wen Tseng, Victor Chiang Liang, Chwen-Ming Liu
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Publication number: 20230387182Abstract: An inductive device includes an insulating layer, a lower magnetic layer, and an upper magnetic layer that are formed such that the insulating layer does not separate the lower magnetic layer and the upper magnetic layer at the outer edges or wings of the inductive device. The lower magnetic layer and the upper magnetic layer form a continuous magnetic layer around the insulating layer and the conductors of the inductive device. Magnetic leakage paths are provided by forming openings through the upper magnetic layer. The openings may be formed through the upper magnetic layer by semiconductor processes that have relatively higher precision and accuracy compared to semiconductor processes for forming the insulating layer such as spin coating. This reduces magnetic leakage path variation within the inductive device and from inductive device to inductive device.Type: ApplicationFiled: August 10, 2023Publication date: November 30, 2023Inventors: Wei-Yu CHOU, Yang-Che CHEN, Chen-Hua LIN, Victor Chiang LIANG, Huang-Wen TSENG, Chwen-Ming LIU
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Publication number: 20230387856Abstract: A method for manufacturing a semiconductor device including an upper-channel implant transistor is provided. The method includes forming one or more fins extending in a first direction over a substrate. The one or more fins include a first region along the first direction and second regions on both sides of the first region along the first direction. A dopant is shallowly implanted in an upper portion of the first region of the fins but not in the second regions and not in a lower portion of the first region of the fins. A gate structure extending in a second direction perpendicular to the first direction is formed overlying the first region of the fins, and source/drains are formed overlying the second regions of the fins, thereby forming an upper-channel implant transistor.Type: ApplicationFiled: July 27, 2023Publication date: November 30, 2023Inventors: Chia-Chung CHEN, Chi-Feng HUANG, Victor Chiang LIANG, Fu-Huan TSAI, Hsieh-Hung HSIEH, Tzu-Jin YEH, Han-Min TSAI, Hong-Lin CHU
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Patent number: 11830889Abstract: A low noise device includes an isolation feature in a substrate. The low noise device further includes a gate stack over a channel in the substrate, wherein the isolation feature is adjacent to the channel. The low noise device further includes a spacer surrounding a portion of the gate stack, wherein an edge of the gate stack is spaced from an edge of the isolation feature adjacent to the spacer by a distance ranging from a minimum spacing distance to about 0.3 microns (?m).Type: GrantFiled: July 23, 2021Date of Patent: November 28, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Victor Chiang Liang, Fu-Huan Tsai, Chi-Feng Huang, Yu-Lin Wei, Fang-Ting Kuo, Meng-Chang Ho
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Publication number: 20230369139Abstract: A method of testing a semiconductor package includes: forming a charge measurement unit over a carrier substrate; forming a first dielectric layer over the charge measurement unit; forming a first metallization layer over the dielectric layer, wherein the forming of the first metallization layer induces first charges to accumulate on the charge measurement unit; performing a first test against the charge measurement unit to determine whether breakdown occurs in the charge measurement unit; and in response to determining that no breakdown occurs in the charge measurement unit, forming a second dielectric layer over the first metallization layer.Type: ApplicationFiled: July 27, 2023Publication date: November 16, 2023Inventors: CHI-HUI LAI, YANG-CHE CHEN, CHEN-HUA LIN, VICTOR CHIANG LIANG, CHWEN-MING LIU
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Patent number: 11804433Abstract: A semiconductor package structure and method of manufacturing a semiconductor package structure are provided. The semiconductor package structure includes a connection layer formed on a metal base layer, at least one die unit formed on the connection layer, a metal pillar connecting the metal base layer and surrounding the die unit, and an interconnect structure overlaid onto the die unit and the metal pillar. Each die unit comprises at least one die attached onto the connection layer and surrounded by a molding structure. The interconnect structure includes a first interconnect layer overlaid onto the die unit and the metal pillar and a second interconnect layer formed on the first interconnect layer. The first and second interconnect layers comprise first and second metal layers being parallel with the top surface of the die unit. A projection of the metal layers overlaps an upper surface of the die.Type: GrantFiled: June 18, 2021Date of Patent: October 31, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Yang-Che Chen, Chen-Hua Lin, Victor Chiang Liang, Huang-Wen Tseng, Chwen-Ming Liu
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Patent number: 11791773Abstract: A method for manufacturing a semiconductor device including an upper-channel implant transistor is provided. The method includes forming one or more fins extending in a first direction over a substrate. The one or more fins include a first region along the first direction and second regions on both sides of the first region along the first direction. A dopant is shallowly implanted in an upper portion of the first region of the fins but not in the second regions and not in a lower portion of the first region of the fins. A gate structure extending in a second direction perpendicular to the first direction is formed overlying the first region of the fins, and source/drains are formed overlying the second regions of the fins, thereby forming an upper-channel implant transistor.Type: GrantFiled: July 12, 2021Date of Patent: October 17, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chia-Chung Chen, Chi-Feng Huang, Victor Chiang Liang, Fu-Huan Tsai, Hsieh-Hung Hsieh, Tzu-Jin Yeh, Han-Min Tsai, Hong-Lin Chu
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Patent number: 11776919Abstract: A semiconductor package includes a multilayer substrate, a device die, an insulating encapsulant, and a shielding structure. The multilayer substrate has a first surface and a second surface opposite to the first surface. The multilayer substrate includes through holes, and each of the through holes extends from the first surface to the second surface. The device die is disposed on the first surface of the multilayer substrate. The insulating encapsulant is disposed on the first surface of the multilayered substrate and encapsulating the device die. The shielding structure is disposed over the first surface of the multilayer substrate. The shielding structure includes a cover body and conductive pillars. The cover body covers the device die and the insulating encapsulant. The conductive pillars are connected to the cover body and fitted into the through holes of the multilayer substrate.Type: GrantFiled: August 5, 2022Date of Patent: October 3, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yang-Che Chen, Victor Chiang Liang, Chen-Hua Lin, Chwen-Ming Liu, Huang-Wen Tseng
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Patent number: 11769698Abstract: A method of testing a semiconductor package is provided. The method includes forming a first metallization layer, wherein the first metallization layer includes a first conductive pad electrically connected to a charge measurement unit and a charge receiving unit; performing a first test against the charge measurement unit through the first conductive pad to determine whether breakdown occurs in the charge measurement unit; and in response to determining that no breakdown occurs in the charge measurement unit, forming a second dielectric layer over the first metallization layer, wherein a portion of the first conductive pad is exposed from the second dielectric layer.Type: GrantFiled: July 16, 2021Date of Patent: September 26, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Chi-Hui Lai, Yang-Che Chen, Chen-Hua Lin, Victor Chiang Liang, Chwen-Ming Liu
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Patent number: 11735485Abstract: A method includes forming a deep well region of a first conductivity type in a substrate, implanting a portion of the deep well region to form a first gate, and implanting the deep well region to form a well region. The well region and the first gate are of a second conductivity type opposite the first conductivity type. An implantation is performed to form a channel region of the first conductivity type over the first gate. A portion of the deep well region overlying the channel region is implanted to form a second gate of the second conductivity type. A source/drain implantation is performed to form a source region and a drain region of the first conductivity type on opposite sides of the second gate. The source and drain regions are connected to the channel region, and overlap the channel region and the first gate.Type: GrantFiled: June 11, 2021Date of Patent: August 22, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chi-Feng Huang, Chia-Chung Chen, Victor Chiang Liang, Mingo Liu
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Patent number: 11721597Abstract: A semiconductor device and a method for detecting a defect in a semiconductor device are provided. The semiconductor device includes a packaging structure. The packaging structure includes a redistribution layer and a detecting component disposed in the redistribution layer. The semiconductor device further includes a cooling plate over the packaging structure and a fixing component penetrating through the packaging structure and the cooling plate. The packaging structure and the cooling plate are fixed by the fixing component. The detecting component is in a chain configuration having a ring shaped structure circling around the fixing component.Type: GrantFiled: August 30, 2021Date of Patent: August 8, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Yang-Che Chen, Chen-Hua Lin, Victor Chiang Liang, Huang-Wen Tseng, Chwen-Ming Liu
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Publication number: 20230215916Abstract: In an embodiment, an integrated circuit (IC) device comprises a semiconductor substrate, an isolation region and an active region disposed on the semiconductor substrate, a gate stack disposed over the active region, and a source and a drain disposed in the active region and interposed by the gate stack in a first direction. The active region is at least partially surrounded by the isolation region. A middle portion of the active region laterally extends beyond the gate stack in a second direction that is perpendicular to the first direction.Type: ApplicationFiled: March 13, 2023Publication date: July 6, 2023Inventors: Ching-Hung Kao, Chi-Feng Huang, Fu-Huan Tsai, Victor Chiang Liang
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Patent number: 11646312Abstract: A method for manufacturing a semiconductor device includes forming one or more fins extending in a first direction over a substrate. The one or more fins include a first region along the first direction and second regions on both sides of the first region along the first direction. A dopant is implanted in the first region of the fins but not in the second regions. A gate structure overlies the first region of the fins and source/drains are formed on the second regions of the fins.Type: GrantFiled: August 16, 2021Date of Patent: May 9, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chia-Chung Chen, Chi-Feng Huang, Victor Chiang Liang, Fu-Huan Tsai, Hsieh-Hung Hsieh, Tzu-Jin Yeh, Han-Min Tsai, Hong-Lin Chu