Patents by Inventor Victor-Chiang Liang
Victor-Chiang Liang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12356684Abstract: A semiconductor structure includes a first gate structure, a second gate structure coupled to the first gate structure, a source region, a first drain region, and a second drain region. The source region is surrounded by the first gate structure and the second gate structure. The first drain region is separated from the source region by the first gate structure. The second drain region is separated from the source region by the second gat structure. A shape of the first drain region and a shape of the second drain region are different from each other from a plan view.Type: GrantFiled: November 14, 2023Date of Patent: July 8, 2025Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Hsing-I Tsai, Fu-Huan Tsai, Chia-Chung Chen, Hsiao-Chun Lee, Chi-Feng Huang, Cho-Ying Lu, Victor Chiang Liang
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Publication number: 20250203994Abstract: A transistor structure includes a field plate structure and a plurality of dielectric structures through the field plate structure. The dielectric structures may be arranged in a grid in a top view of the transistor structure. The dielectric structures enable the field plate structure to be positioned closer to a gate structure of the transistor than without the dielectric structures, which enables the length of the field plate structure to be increased without increasing the overall length (or with minimal length increase) of the transistor.Type: ApplicationFiled: January 4, 2024Publication date: June 19, 2025Inventors: Jyun-Guan JHOU, Po-Chih SU, Pei-Lun WANG, Wan-Jyun SYUE, Victor Chiang LIANG, Yu-Chang JONG
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Publication number: 20250174499Abstract: A method of testing a semiconductor package includes: attaching a charge measurement unit to a carrier substrate; forming a first metallization layer over the charge measurement unit, wherein the forming of the first metallization layer induces first charges to accumulate on the charge measurement unit; performing a first test against the charge measurement unit to determine whether breakdown occurs in the charge measurement unit; and in response to determining that no breakdown occurs in the charge measurement unit, forming a second metallization layer over the first metallization layer.Type: ApplicationFiled: January 23, 2025Publication date: May 29, 2025Inventors: CHI-HUI LAI, YANG-CHE CHEN, CHEN-HUA LIN, VICTOR CHIANG LIANG, CHWEN-MING LIU
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Publication number: 20250098294Abstract: In a method of fabricating an electronic device, a first nMOS device structure and a second nMOS device structure are formed. Each nMOS device structure includes a gate oxide disposed on a p-type base material and a gate disposed on the gate oxide. N-type dopant implantation is performed to form source and drain regions in the p-type substate of the first nMOS device structure and source and drain regions in the p-type substate of the second nMOS device structure, and to further dope the gate of the first nMOS device structure n-type to form a first nMOS device with the gate doped n-type. P-type dopant implantation is performed to dope the gate of the second nMOS device structure p-type to form the second nMOS device structure with the gate anti-doped p-type.Type: ApplicationFiled: September 15, 2023Publication date: March 20, 2025Inventors: Chia-Cheng Ho, Chia-Yu Wei, Po-Yu Chiang, Victor Chiang Liang
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Publication number: 20250087553Abstract: A method includes forming a solder layer on a surface of one or more chips. A lid is positioned over the solder layer on each of the one or more chips. Heat and pressure are applied to melt the solder layer and attach each lid to a corresponding solder layer. The solder layer has a thermal conductivity of ?50 W/mK.Type: ApplicationFiled: November 22, 2024Publication date: March 13, 2025Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yang-Che CHEN, Chen-Hua LIN, Huang-Wen TSENG, Victor Chiang LIANG, Chwen-Ming LIU
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Patent number: 12243788Abstract: A method of testing a semiconductor package includes: forming a charge measurement unit over a carrier substrate; forming a first dielectric layer over the charge measurement unit; forming a first metallization layer over the dielectric layer, wherein the forming of the first metallization layer induces first charges to accumulate on the charge measurement unit; performing a first test against the charge measurement unit to determine whether breakdown occurs in the charge measurement unit; and in response to determining that no breakdown occurs in the charge measurement unit, forming a second dielectric layer over the first metallization layer.Type: GrantFiled: July 27, 2023Date of Patent: March 4, 2025Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Chi-Hui Lai, Yang-Che Chen, Chen-Hua Lin, Victor Chiang Liang, Chwen-Ming Liu
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Patent number: 12191811Abstract: A method for manufacturing a semiconductor device including an upper-channel implant transistor is provided. The method includes forming one or more fins extending in a first direction over a substrate. The one or more fins include a first region along the first direction and second regions on both sides of the first region along the first direction. A dopant is shallowly implanted in an upper portion of the first region of the fins but not in the second regions and not in a lower portion of the first region of the fins. A gate structure extending in a second direction perpendicular to the first direction is formed overlying the first region of the fins, and source/drains are formed overlying the second regions of the fins, thereby forming an upper-channel implant transistor.Type: GrantFiled: July 27, 2023Date of Patent: January 7, 2025Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chia-Chung Chen, Chi-Feng Huang, Victor Chiang Liang, Fu-Huan Tsai, Hsieh-Hung Hsieh, Tzu-Jin Yeh, Han-Min Tsai, Hong-Lin Chu
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Patent number: 12183655Abstract: A method includes forming a solder layer on a surface of one or more chips. A lid is positioned over the solder layer on each of the one or more chips. Heat and pressure are applied to melt the solder layer and attach each lid to a corresponding solder layer. The solder layer has a thermal conductivity of ?50 W/mK.Type: GrantFiled: July 26, 2022Date of Patent: December 31, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yang-Che Chen, Chen-Hua Lin, Huang-Wen Tseng, Victor Chiang Liang, Chwen-Ming Liu
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Publication number: 20240312851Abstract: A semiconductor package includes a semiconductor chip disposed over a first main surface of a first substrate, a package lid disposed over the semiconductor chip, and spacers extending from the package lid through corresponding holes in the first substrate. The spacers enter the holes at a first main surface of the first substrate and extend beyond an opposing second main surface of the first substrate.Type: ApplicationFiled: May 22, 2024Publication date: September 19, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yang-Che CHEN, Chen-Hua LIN, Huang-Wen TSENG, Victor Chiang LIANG, Chwen-Ming LIU
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Publication number: 20240290652Abstract: A semiconductor device includes a first gate stack structure over a substrate, a source/drain epitaxial layer, a lightly doped region, and a silicide region. The source/drain epitaxial layer is disposed in the substrate and adjacent to the first gate stack structure. The lightly doped region is located in the substrate to be electrically connected to the source/drain epitaxial layer. The lightly doped region includes a first portion protrudes from a sidewall of the source/drain epitaxial layer. The silicide region is in contact with a top surface and sidewalls of a top portion of the source/drain epitaxial layer and a top surface of the first portion of the lightly doped region. The top portion of the source/drain epitaxial layer is higher than the top surface of the first portion of the lightly doped region.Type: ApplicationFiled: May 7, 2024Publication date: August 29, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chia-Chung Chen, Chi-Feng Huang, Victor Chiang Liang, Chung-Hao Chu, Ching-Yu Yang
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Publication number: 20240262681Abstract: A micro electro mechanical system (MEMS) includes a circuit substrate, a first MEMS structure disposed over the circuit substrate, and a second MEMS structure disposed over the first MEMS structure.Type: ApplicationFiled: April 19, 2024Publication date: August 8, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yang-Che CHEN, Victor Chiang LIANG, Chen-Hua LIN, Chwen-Ming LIU, Huang-Wen TSENG, Yi-Chuan TENG
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Publication number: 20240223087Abstract: A method of making a semiconductor device includes implanting a source/drain (S/D) in the substrate adjacent to a gate structure. The method further includes implanting a lightly doped drain (LDD) region in the substrate in direct contact with the S/D, wherein a dopant concentration in the LDD region is less than a dopant concentration in the S/D. The method further includes implanting a doping extension region in the substrate in direct contact with the LDD region, wherein a maximum depth of the doping extension region is 10-times to 30-times greater than a maximum depth of the LDD.Type: ApplicationFiled: March 18, 2024Publication date: July 4, 2024Inventors: Chu Fu CHEN, Chi-Feng HUANG, Chia-Chung CHEN, Chin-Lung CHEN, Victor Chiang LIANG, Chia-Cheng PAO
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Patent number: 12027433Abstract: A semiconductor package includes a semiconductor chip disposed over a first main surface of a first substrate, a package lid disposed over the semiconductor chip, and spacers extending from the package lid through corresponding holes in the first substrate. The spacers enter the holes at a first main surface of the first substrate and extend beyond an opposing second main surface of the first substrate.Type: GrantFiled: August 10, 2022Date of Patent: July 2, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yang-Che Chen, Chen-Hua Lin, Huang-Wen Tseng, Victor Chiang Liang, Chwen-Ming Liu
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Patent number: 11993512Abstract: A micro electro mechanical system (MEMS) includes a circuit substrate, a first MEMS structure disposed over the circuit substrate, and a second MEMS structure disposed over the first MEMS structure.Type: GrantFiled: March 14, 2022Date of Patent: May 28, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yang-Che Chen, Victor Chiang Liang, Chen-Hua Lin, Chwen-Ming Liu, Huang-Wen Tseng, Yi-Chuan Teng
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Patent number: 11996323Abstract: A semiconductor device includes a plurality of gate electrodes over a substrate, and a source/drain epitaxial layer. The source/drain epitaxial layer is disposed in the substrate and between two adjacent gate electrodes, wherein a bottom surface of the source/drain epitaxial layer is buried in the substrate to a depth less than or equal to two-thirds of a spacing between the two adjacent gate electrodes.Type: GrantFiled: July 27, 2022Date of Patent: May 28, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chia-Chung Chen, Chi-Feng Huang, Victor Chiang Liang, Chung-Hao Chu, Ching-Yu Yang
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Patent number: 11990474Abstract: A method of fabricating a semiconductor device includes forming a gate structure, a first edge structure and a second edge structure on a semiconductor strip. The method further includes forming a first source/drain feature between the gate structure and the first edge structure. The method further includes forming a second source/drain feature between the gate structure and the second edge structure, wherein a distance between the gate structure and the first source/drain feature is different from a distance between the gate structure and the second source/drain feature. The method further includes implanting a buried channel in the semiconductor strip, wherein the buried channel is entirely below a top-most surface of the semiconductor strip, a maximum depth of the buried channel is less than a maximum depth of the first source/drain feature, and a dopant concentration of the buried channel is highest under the gate structure.Type: GrantFiled: January 9, 2023Date of Patent: May 21, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Shu Fang Fu, Chi-Feng Huang, Chia-Chung Chen, Victor Chiang Liang, Fu-Huan Tsai
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Patent number: 11973113Abstract: Provided is a semiconductor device including a substrate having a lower portion and an upper portion on the lower portion; an isolation region disposed on the lower portion of the substrate and surrounding the upper portion of the substrate in a closed path; a gate structure disposed on and across the upper portion of the substrate; source and/or drain (S/D) regions disposed in the upper portion of the substrate at opposite sides of the gate structure; and a channel region disposed below the gate structure and abutting between the S/D regions, wherein the channel region and the S/D regions have different conductivity types, and the channel region and the substrate have the same conductivity type.Type: GrantFiled: July 29, 2022Date of Patent: April 30, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chia-Chung Chen, Chi-Feng Huang, Victor Chiang Liang, Chung-Hao Chu
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Patent number: 11936299Abstract: A transistor includes a gate structure over a substrate, wherein the substrate includes a channel region. The transistor further includes a source/drain (S/D) in the substrate adjacent to the gate structure. The transistor further includes a lightly doped drain (LDD) region adjacent to the S/D, wherein a dopant concentration in the first LDD is less than a dopant concentration in the S/D. The transistor further includes a doping extension region adjacent the LDD region, wherein the doping extension region extends farther under the gate structure than the LDD region, and a maximum depth of the doping extension region is 10-times to 30-times greater than a maximum depth of the LDD.Type: GrantFiled: September 21, 2020Date of Patent: March 19, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chu Fu Chen, Chi-Feng Huang, Chia-Chung Chen, Chin-Lung Chen, Victor Chiang Liang, Chia-Cheng Pao
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Publication number: 20240088224Abstract: A semiconductor structure includes a first gate structure, a second gate structure coupled to the first gate structure, a source region, a first drain region, and a second drain region. The source region is surrounded by the first gate structure and the second gate structure. The first drain region is separated from the source region by the first gate structure. The second drain region is separated from the source region by the second gat structure. A shape of the first drain region and a shape of the second drain region are different from each other from a plan view.Type: ApplicationFiled: November 14, 2023Publication date: March 14, 2024Inventors: HSING-I TSAI, FU-HUAN TSAI, CHIA-CHUNG CHEN, HSIAO-CHUN LEE, CHI-FENG HUANG, CHO-YING LU, VICTOR CHIANG LIANG
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Patent number: 11908884Abstract: An inductive device includes an insulating layer, a lower magnetic layer, and an upper magnetic layer that are formed such that the insulating layer does not separate the lower magnetic layer and the upper magnetic layer at the outer edges or wings of the inductive device. The lower magnetic layer and the upper magnetic layer form a continuous magnetic layer around the insulating layer and the conductors of the inductive device. Magnetic leakage paths are provided by forming openings through the upper magnetic layer. The openings may be formed through the upper magnetic layer by semiconductor processes that have relatively higher precision and accuracy compared to semiconductor processes for forming the insulating layer such as spin coating. This reduces magnetic leakage path variation within the inductive device and from inductive device to inductive device.Type: GrantFiled: April 7, 2022Date of Patent: February 20, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Wei-Yu Chou, Yang-Che Chen, Chen-Hua Lin, Victor Chiang Liang, Huang-Wen Tseng, Chwen-Ming Liu