Abstract: A storage cell circuit (11) comprises a voltage reduction circuit (17), a latch (18), and a tri-state driver circuit (19). The latch (18) has a terminal (14) and a terminal (16) for providing data stored therein. The voltage reduction circuit (17) couples to the power terminal of the latch (18) and reduces the voltage powering the latch. The tri-state driver circuit (19) has a clock input (12), a data input (13), a terminal coupled to the terminal (14), and a terminal coupled to the terminal (16). A clock signal applied to the clock input (12) has a first phase and a second phase. During the first phase of the clock, the terminals of the tri-state driver circuit (19) are at a high impedance leaving the data stored in the latch (18) undisturbed. During the second phase of the clock, the tri-state driver circuit (19) provides complementary signals of a data signal applied to the data input (13) for writing to the latch (18).

Abstract: A one shot circuit having feedback from the output to an input gate is provided to inhibit the input gate when an output is being provided. This feedback inhibits the input gate thereby preventing noise on the input from falsely triggering the one shot. A capacitor in conjunction with a Schmitt trigger is used to determine output pulse width. The output pulse width can be increased by adding additional capacitance to the first capacitor which is fully integrated on an integrated circuit chip. A reset input is also provided so that the circuit can be reset upon command.