Patents by Inventor Victor E. Lee

Victor E. Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11410176
    Abstract: Systems and methods for enhanced detection of fraudulent electronic transactions are disclosed. In one embodiment, a system uses the ongoing stream of transactions to construct and maintain a dynamically evolving merchant relationship graph. When a proposed transaction is submitted to the system, the system computes a predicted likelihood that the given account would make a transaction with these characteristics with the given merchant. The graph is used to compute transitive relatedness between merchants which may be indirectly associated with one another, as well as to compute aggregate relatedness, when there are multiple avenues of relationship between two merchants.
    Type: Grant
    Filed: June 25, 2015
    Date of Patent: August 9, 2022
    Assignee: TIGERGRAPH, INC.
    Inventors: Ruoming Jin, Ming Lin, Yu Xu, Adam P. Anthony, Victor E. Lee
  • Publication number: 20150379517
    Abstract: Systems and methods for enhanced detection of fraudulent electronic transactions are disclosed. In one embodiment, a system uses the ongoing stream of transactions to construct and maintain a dynamically evolving merchant relationship graph. When a proposed transaction is submitted to the system, the system computes a predicted likelihood that the given account would make a transaction with these characteristics with the given merchant. The graph is used to compute transitive relatedness between merchants which may be indirectly associated with one another, as well as to compute aggregate relatedness, when there are multiple avenues of relationship between two merchants.
    Type: Application
    Filed: June 25, 2015
    Publication date: December 31, 2015
    Inventors: Ruoming Jin, Ming Lin, Yu Xu, Adam P. Anthony, Victor E. Lee
  • Patent number: 6671836
    Abstract: A method and apparatus for testing DRAM is described. The method and apparatus causes the DRAM pins to be reconfigured to provide a direct path between the memory core and the DRAM pins. This reconfiguration allows the memory core to be “seen” without probing and also allows faster and simpler testing with a more traditional protocol. The method and apparatus for testing also provides for several options to further increase testing speed. These options include an internal block compare and a core noise option. The internal block compare performs an internal parallel bit by bit comparison of read data to the contents of a write buffer and generates an error signal if a mismatch occurs. The core noise option simulates the noise that can occur during the normal mode of operation that does not occur during testing.
    Type: Grant
    Filed: September 23, 1999
    Date of Patent: December 30, 2003
    Assignee: Rambus Inc.
    Inventors: Lawrence Lai, Victor E. Lee, James A. Gasbarro