Patents by Inventor Victor Emmanuel Stephanus Van Dijk

Victor Emmanuel Stephanus Van Dijk has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7515074
    Abstract: A method for coding information in an electronic circuit and an electronic circuit for coding information uses at least two electrically coupled signal paths (X0, X1). Cross-talk between two electrically coupled signal paths (X0, X1) can be utilized to perform logical computation. A signal is propagating on two signal paths (X0, X1) in the form of either rising or falling transitions. The relative delay between the transitions on the two paths (X0, X1) determines the logic value of the output signal (X) to be produced. If the signal on the first paths (X0) propagates faster than the signal on the second path (X1), an output signal (X) having a first logic value is produced. If the signal on the second path (X1) propagates faster than the signal on the first path (X0). an output signal (X) having a second logic value is produced.
    Type: Grant
    Filed: August 6, 2003
    Date of Patent: April 7, 2009
    Assignee: NXP B.V.
    Inventors: Francesco Pessolano, Victor Emmanuel Stephanus Van Dijk
  • Patent number: 7006701
    Abstract: A method for compressing a sequence of digital images includes: comparing a reference image of the sequence of digital images to a subsequent image of the sequence of digital images. In response to the reference and subsequent images being the same within a predetermined threshold, 1) a count of a number of images discarded is incremented, 2) the subsequent image is discarded, and 3) the comparing step is repeated with a next subsequent image. In response to the reference and subsequent images not being within the predetermined threshold, 1) the count is initialized and 2) the comparing step is repeated using the subsequent image as the reference image. Rather than comparing whole images corresponding portions of the images can be compared and compressed independently.
    Type: Grant
    Filed: October 9, 2002
    Date of Patent: February 28, 2006
    Assignee: Koninklijke Philips Electronics N.V.
    Inventors: Victor Emmanuel Stephanus van Dijk, Francesco Pessolano
  • Patent number: 6914468
    Abstract: The invention relates to a controllable delay circuit for delaying an electrical input signal wherein the controllable delay circuit is arranged for receiving an input signal and at least one control signal, wherein, in use, the delay circuit delays the input signal by a delay for generating an output signal, wherein the delay is a function of the at least one control signal, wherein the delay circuit comprises a first module for generating a base signal and at least one support signal on the basis of the input signal and the at least one control signal, wherein, in use, the phase and/or the amplitude of the at least one support signal is controllable with respect to the phase and/or the amplitude of the base-signal by means of the at least one control signal, wherein the delay circuit also comprises a second module connected to the first module, which second module comprises a signal-conductor and at least one support conductor, wherein the signal conductor and the at least one support conductor extend, at l
    Type: Grant
    Filed: June 4, 2002
    Date of Patent: July 5, 2005
    Assignee: Koninklijke Philips Electronics N.V.
    Inventors: Victor Emmanuel Stephanus Van Dijk, Rinze Ida Mechtildis Peter Meijer, Hendricus Joseph Maria Veendrick
  • Publication number: 20040150451
    Abstract: The invention relates to a controllable delay circuit for delaying an electrical input signal wherein the controllable delay circuit is arranged for receiving an input signal and at least one control signal, wherein, in use, the delay circuit delays the input signal by a delay for generating an output signal, wherein the delay is a function of the at least one control signal, wherein the delay circuit comprises a first module for generating a base signal and at least one support signal on the basis of the input signal and the at least one control signal, wherein, in use, the phase and/or the amplitude of the at least one support signal is controllable with respect to the phase and/or the amplitude of the base-signal by means of the at least one control signal, wherein the delay circuit also comprises a second module connected to the first module, which second module comprises a signal-conductor and at least one support conductor, wherein the signal conductor and the at least one support conductor extend, at l
    Type: Application
    Filed: December 3, 2003
    Publication date: August 5, 2004
    Inventors: Victor Emmanuel Stephanus Van Dijk, Rinze Ida Mechtildis Peter Meijer, Hendricus Joseph Maria Veendrick
  • Publication number: 20040071353
    Abstract: A method for compressing a sequence of digital images includes: comparing a reference image of the sequence of digital images to a subsequent image of the sequence of digital images. In response to the reference and subsequent images being the same within a predetermined threshold, 1) a count of a number of images discarded is incremented, 2) the subsequent image is discarded, and 3) the comparing step is repeated with a next subsequent image. In response to the reference and subsequent images not being within the predetermined threshold, 1) the count is initialized and 2) the comparing step is repeated using the subsequent image as the reference image. Rather than comparing whole images corresponding portions of the images can be compared and compressed independently.
    Type: Application
    Filed: October 9, 2002
    Publication date: April 15, 2004
    Applicant: KONINKLIJKE PHILIPS ELECTRONICS N.V.
    Inventors: Victor Emmanuel Stephanus van Dijk, Francesco Pessolano