Abstract: A decoder circuit, for example a dual-rail decoder, receives input signals (43) from the end of a communications bus (not shown). The parity is calculated over the data wires (Do, D1, D2, D3) using exclusive OR gates (45, 47, and 49). The calculated data parity signal (51) is compared with a transmitted parity signal (53) (shown as “carry”) in an exclusive OR gate (55). Rather than connecting the control signal (57) from the exclusive OR gate (55) directly to the multiplexers (590, 591, 592, 593), the control signal (57) is instead connected to a gating circuit (71). The gating circuit (71), for example a AND gate, receives the control signal (57) as a first input signal. The gating circuit (71) also receives a second input signal in the form of a gating control signal (73). The gating control signal (73) is delayed by a predetermined amount, for example corresponding to the worst case delay of the signals in the input data signals (43).

Abstract: The present invention relates to a method for coding information in an electronic circuit and an electronic circuit for coding information, said circuit comprising at least two electrically coupled signal paths (X0, X1). The invention is based on the idea that cross-talk between two electrically coupled signal paths (X0, X1) can be utilized to perform logical computation. A signal is propagating on two signal paths (X0, X1) in the form of either rising or falling transitions. The relative delay between the transitions on the two paths (X0, X1) determines the logic value of the output signal (X) to be produced. If the signal on the first paths (X0) propagates faster than the signal on the second path (X1), an output signal (X) having a first logic value is produced. If the signal on the second path (X1) propagates faster than the signal on the first path (X0), an output signal (X) having a second logic value is produced.

Abstract: An electronic device has a data communication bus (200) mounted on a semiconductor substrate (120). The data communication bus (200) has a first conductor (102), a second conductor (104), a third conductor (106) and a fourth conductor (108). The conductors have been reordered and the distances (I1, I2, I3) between two neighboring conductors have been recalculated on the basis of the correlation between the data-bits conveyed by the conductors of the data communication bus (200), e.g. the number of times that the two transitions on two conductors have a predetermined value out of the total number of transitions on that conductor pair. Consequently, a data communication bus (200) is obtained in which the power consumption resulting from the charging of the cross-coupling capacitance between two neighboring conductors is reduced.