Abstract: An Integrated circuit (IC) device accommodating a circuit and associated control module, being operative to determine an apparatus characteristic in accordance with one out of few selectable characteristics. The circuit is operative in conjunction with more than three of a plurality of external passive circuits corresponding to the plurality of apparatus characteristics, and includes (N?1) digital I/O pins. The control module is operative to: (i) in response to a series of triggering signals, generate samples of the digital I/O pin's state that correspond to a plurality of different sequences of states when each of the plurality of external circuits is respectively applied to the pin and (ii) determining, from the samples, which of the plurality of different sequences of states has occurred that corresponds to the individual external circuit that has been applied to the pin; and (iii) determining an individual apparatus characteristic which corresponds to the determined sequence.

Abstract: An Integrated circuit (IC) device accommodating a circuit and associated control module, being operative to determine an apparatus characteristic in accordance with one out of few selectable characteristics. The circuit is operative in conjunction with more than three of a plurality of external passive circuits corresponding to the plurality of apparatus characteristics, and includes (N?1) digital I/O pins. The control module is operative to: (i) in response to a series of triggering signals, generate samples of the digital I/O pin's state that correspond to a plurality of different sequences of states when each of the plurality of external circuits is respectively applied to the pin and (ii) determining, from the samples, which of the plurality of different sequences of states has occurred that corresponds to the individual external circuit that has been applied to the pin; and (iii) determining an individual apparatus characteristic which corresponds to the determined sequence.

Abstract: A processor, comprising a processing unit having an active state and a sleep state in which at least one of its sub-sections is inactive and a communication port adapted to receive signals from external units over a bus, which is configured to be not fully operative when the processor is in the sleep state. The processor additionally includes a bus monitoring unit configured to stall the bus responsive to identifying transmissions on the bus directed to the communication port, while the processing unit is in the sleep state and to indicate to the communication port that a transmission started while it was in the sleep state.

Abstract: A processor, comprising a processing unit having an active state and a sleep state in which at least one of its sub-sections is inactive and a communication port adapted to receive signals from external units over a bus, which is configured to be not fully operative when the processor is in the sleep state. The processor additionally includes a bus monitoring unit configured to stall the bus responsive to identifying transmissions on the bus directed to the communication port, while the processing unit is in the sleep state and to indicate to the communication port that a transmission started while it was in the sleep state.

Abstract: A processor having a core configured to control a keyboard and a plurality of pins connected to the core, configured to transfer signals from the processor to the keyboard. A controller is configured to transfer signals from one or more registers through at least one of the pins, intermittently with signals transferred to the keyboard.

Abstract: An improved system is described for allowing an embedded controller and a host processor to share access to modules in a computer system. The shared access system of the present invention enables exclusive, one-at-a-time access by a processor to a module and concurrent access by more than one processor to a module. An internal bus with two power sources is used to allow continued access by one of the processors when one of the two power sources is not providing power. Asynchronous clocking is provided to allow increased throughput to modules. An example of a protocol that allows an embedded controller to access more than one module is also described.

Abstract: A receiver includes a single infrared (IR) sensor, which is coupled to sense an IR signal carrying data and to produce an electrical signal responsively to the IR signal. The receiver further includes multiple receiver channels arranged to accept the electrical signal from the single IR sensor, each receiver channel configured to process the electrical signal in accordance with a different, respective IR remote control protocol so as to extract the data, and to output the extracted data to a host system.

Abstract: A processor, comprising a processing unit having an active state and a sleep state in which at least one of its sub-sections is inactive and a communication port adapted to receive signals from external units over a bus, which is configured to be not fully operative when the processor is in the sleep state. The processor additionally includes a bus monitoring unit configured to stall the bus responsive to identifying transmissions on the bus directed to the communication port, while the processing unit is in the sleep state and to indicate to the communication port that a transmission started while it was in the sleep state.

Abstract: A method for processing a signal envelope generated by demodulating a received signal that includes a train of pulses that is transmitted at a carrier frequency and is modulated at a given baud rate with data symbols in accordance with a predetermined communication protocol, which defines features of the modulated signal. The method includes measuring a duration of a selected feature in the signal envelope as defined by the communication protocol. The baud rate of the signal is estimated based on the measured duration without counting the pulses in the received signal. The data symbols are decoded by processing the signal envelope responsively to the estimated baud rate.

Abstract: A processor having a core configured to control a keyboard and a plurality of pins connected to the core, configured to transfer signals from the processor to the keyboard. A controller is configured to transfer signals from one or more registers through at least one of the pins, intermittently with signals transferred to the keyboard.

Abstract: A master/slave system architecture that includes a single wire bus, a master device and bus interface coupled to the bus. The system further includes plurality of slave devices having respective bus interfaces coupled to the bus. Each of the slave devices having a designated device identification. There is further provided a communication protocol implemented over the single wire bus and employed by the master and the slave devices. The protocol includes bus transactions composed each of bit signals that belong each to a bit signal type from among a plurality of bit signal types. Each bit signal type has a time interval that is discernible from respective time intervals of all other bit signal types from among the plurality of bit signal types.

Abstract: Apparatus for demodulating a train of pulses includes a one-shot device having an asynchronous data input terminal, which is configured to receive the train of pulses, and a one-shot data output terminal. A first clocked logic gate has a first clocked data input terminal, which is coupled to the one-shot data output terminal, and a first clocked data output terminal. A combinatorial logic gate has combinatorial input terminals, which are coupled to the one-shot and first clocked data output terminals, and a combinatorial output terminal. A second clocked logic gate has a second clocked data input terminal, which is coupled to the combinatorial output terminal, and a second clocked data output terminal, which is configured to output a demodulated envelope of the train of pulses.

Abstract: A receiver includes a single infrared (IR) sensor, which is coupled to sense an IR signal carrying data and to produce an electrical signal responsively to the IR signal. The receiver further includes multiple receiver channels arranged to accept the electrical signal from the single IR sensor, each receiver channel configured to process the electrical signal in accordance with a different, respective IR remote control protocol so as to extract the data, and to output the extracted data to a host system.

Abstract: Apparatus for demodulating a train of pulses includes a one-shot device having an asynchronous data input terminal, which is configured to receive the train of pulses, and a one-shot data output terminal. A first clocked logic gate has a first clocked data input terminal, which is coupled to the one-shot data output terminal, and a first clocked data output terminal. A combinatorial logic gate has combinatorial input terminals, which are coupled to the one-shot and first clocked data output terminals, and a combinatorial output terminal. A second clocked logic gate has a second clocked data input terminal, which is coupled to the combinatorial output terminal, and a second clocked data output terminal, which is configured to output a demodulated envelope of the train of pulses.

Abstract: A method for processing a signal envelope generated by demodulating a received signal that includes a train of pulses that is transmitted at a carrier frequency and is modulated at a given baud rate with data symbols in accordance with a predetermined communication protocol, which defines features of the modulated signal. The method includes measuring a duration of a selected feature in the signal envelope as defined by the communication protocol. The baud rate of the signal is estimated based on the measured duration without counting the pulses in the received signal. The data symbols are decoded by processing the signal envelope responsively to the estimated baud rate.

Abstract: Disclosed herein are methods and systems for controlling fan speed by approximating a nonlinear temperature control function activated within a given temperature control range. The temperature control range is divided into numerous linear segments each of which is associated with a sub-range of temperatures and may approximate a segment of the control function. Control coefficients may be determined for each of the linear segments. The controlled temperature is measured and used for determining a corresponding sub-range, and a linear segment. A control signal may be calculated according to the control coefficients of the segment determined by the measured temperature. The control signal is used for the activation of one or more fans, and is continuously determined for new measured temperatures.

Abstract: A master/slave system architecture including a single wire bus and master device and bus interface coupled to the bus. The system further includes slave devices having respective bus interfaces coupled to the bus. The system further includes a communication protocol implemented over the single wire bus and employed by the master and the slave devices. The protocol includes bus transactions for communicating between the master and the slave devices. The communication protocol further includes Master Slave Operational Interface (MSOI) that includes repertoire of functions properties stored in the master device, whereby, the master can communicate with any slave device that supports functions properties that belong to the repertoire of functions properties, using the bus transactions, substantially without need of retrofit.

Abstract: An apparatus and method is disclosed for providing a fast, low power consumption, detection of at least one depressed key in a resistive matrix keyboard. The common contact of each row of a resistive matrix is connected to a first input of each of a plurality of analog/digital comparators capable of switching between high and low voltage states. A common predetermined reference voltage is applied to a second input of each analog/digital comparator using a digital to analog converter. The output of a analog/digital comparator is in a first state if the voltage level applied to the first input is higher than the reference voltage, and in a second state if the voltage level applied to the first input is lower than the reference voltage. The reference voltage is varied to identify which analog/digital comparator has experienced a change of state.

Abstract: An improved system is described for allowing an embedded controller and a host processor to share access to modules in a computer system. The shared access system of the present invention enables exclusive, one-at-a-time access by a processor to a module and concurrent access by more than one processor to a module. An internal bus with two power sources is used to allow continued access by one of the processors when one of the two power sources is not providing power. Asynchronous clocking is provided to allow increased throughput to modules. An example of a protocol that allows an embedded controller to access more than one module is also described.

Abstract: An apparatus and method is disclosed for providing a fast, low power consumption, detection of at least one depressed key in a resistive matrix keyboard. The common contact of each row of a resistive matrix is connected to a first input of each of a plurality of analog/digital comparators capable of switching between high and low voltage states. A common predetermined reference voltage is applied to a second input of each analog/digital comparator using a digital to analog converter. The output of a analog/digital comparator is in a first state if the voltage level applied to the first input is higher than the reference voltage, and in a second state if the voltage level applied to the first input is lower than the reference voltage. The reference voltage is varied to identify which analog/digital comparator has experienced a change of state.