Abstract: A receiver for VSB signals includes tuner channel changing circuitry. AGC circuitry, an IF FPLL and confidence counters, for indicating when signal acquisition or loss occurs. When a loss of signal indication is generated, the IF FPLL is reset, but not the tuner channel changing circuitry and the AGC circuitry, in order to quickly reacquire the signal. If the loss of signal indication persists for a predetermined time or for a predetermined number of loss of signal indications, the IF FPLL, the tuner channel changing circuitry and the AGC circuitry are all reset to reacquire the signal.

Abstract: A bandwidth stabilized PLL in an FPLL has an I channel including an I channel signal, having a pilot, and a Q channel signal. The DC offset, including the pilot, of the I channel signal is determined. The value of the pilot is found by subtracting the determined DC offset from the I channel signal. An error signal is developed from the known value of the transmitted pilot and the determined value of the pilot. The error signal is used to control a gain block for the Q channel for stabilizing the bandwidth of the PLL. Different embodiments are shown for controlling the gain of the PLL from both inside and outside of the PLL.

Abstract: A television receiver includes a tuner for receiving either analog or digital signals. Separate analog and digital demodulators are selectively coupled to the tuner through an RF switch that is controlled by the signal from a sync detector in the output of the analog demodulator. The selected one of the demodulators develops an AGC signal that is coupled to the tuner through a current mirror. Operating potential for the demodulators is coupled through the RF switch so that the oscillator in the non-selected demodulator is disabled and precluded from interfering with the oscillator in the enabled demodulator.

Abstract: A linear filter for use in 8 MHZ television broadcast systems is provided having a frequency response which includes a notch corresponding to a television picture carrier fpix, a notch corresponding to approximately a television color subcarrier fcs, and a notch corresponding to approximately a television sound carrier fs. Accordingly, the linear filter substantially reduces co-channel interference in a digital signal received by a digital television.

Abstract: An HDTV receiver includes an AGC system that develops an RF AGC voltage that is derived on an analog basis and an IF AGC voltage that is derived on a digital basis. The digital voltage is developed from an error signal that comprises the most significant bits of a continuously operated large accumulator that is supplied with the algebraically combined output of the digital signal and an AGC reference number.

Abstract: A FPLL has an I, a Q and a third multiplier, with the I multiplier supplying demodulated signals to a limiter and the Q multiplier supplying signals to a loop filter. A VCO and phase shift circuit supply quadrature signals to the I and Q multipliers. The analog input signal is applied to the I multiplier and to the third multiplier. The third multiplier, which is located in an AC path in the loop to avoid the effects of offsets due to stray DC voltages and currents, is also supplied with the digital output of the limiter. The third multiplier supplies its output to the Q multiplier.

Abstract: A biphase stable FPLL includes a lock switch, operated in response to a frequency lock condition, that forces a predetermined voltage on the input of the third multiplier to guarantee that the loop locks up in a phase that produces a desired polarity of demodulated signal. A frequency lock indicator operates the lock switch to force the predetermined voltage on the third multiplier irrespective of the actual lock up phase of the loop. If the lock up phase is wrong, the voltage reversal causes the VCO to slip 180.degree. in phase and the loop locks up in its other bistable state.

Abstract: An AFC filter for an FPLL comprises a filter formed of a network of resistors and capacitors exhibiting a predetermined phase response characteristic. The phase response characteristic is limited with increasing frequency to a value of about 90.degree. during a start-up interval.

Abstract: A bi-phase stable FPLL is locked by a DC pilot component in a recovered data signal. The signal is formatted in repetitive data segments including sync characters and a DC pilot. A sign bit, indicative of the polarity of the recovered data, is developed from the sync characters and is used to augment the DC pilot to stabilize the lock up of the FPLL to produce the desired polarity of recovered data.

Abstract: A dual mode AGC system for a television receiver in which data is in the form of symbols occurring at a fixed symbol rate. The symbols are sent in successive data segments, each having a sync character. Enablement of an AFC Defeat signal defines an initial interval during which the IF gain is maximum. When the AFC Defeat signal becomes inactive, the receiver is operated in a non-coherent mode in which the gain of the IF amplifier is reduced incrementally whenever the IF signal exceeds a clipping level for a period of eight successive symbol clocks. Upon a segment sync lock condition occurring, a normal coherent mode is entered in which the AGC responds to a signal characteristic, i.e. data segment sync. The rate of gain change available in the non-coherent mode-is much greater than that in the normal coherent mode.

Abstract: A low phase noise, high frequency low voltage integrated circuit oscillator has a minimum number of live pins. It includes a three transistor current mirror defining a voltage node and a current node with an emitter follower transistor coupled between the voltage node and the current node. An output is taken from the emitter follower transistor and a tuned circuit is coupled to the voltage node. A pair of power supply pins are provided for power application to the integrated circuit and one live pin is coupled to the voltage node. A tuning circuit for affecting capacitance changes for varying the frequency of the oscillator is connectable to the voltage node. In some versions of the oscillator that use a separate crystal, additional pins are needed.

Abstract: A synchronous demodulator is controlled by a phase locked loop for tuning to a pilot in a television signal. A start-up interval is commenced upon initiation of tuning (either after power-up or a channel change) during which a substitute signal at the pilot frequency is supplied to the phase locked loop to rapidly bring the VCO close to its lock-up frequency. Thereafter the IF signal is supplied. The start-up interval is defined by an AFC Defeat signal from a microprocessor and controls an IF switch. The substitute signal is from a crystal oscillator.

Abstract: A highly accurate, inexpensive digital to analog converter requiring minimal accuracy in component values. A digital word is received serially, the least significant bit first. A voltage is stored on a capacitor at each bit, the value of the voltage being halfway between a reference voltage and the previously stored voltage, the reference voltage value depending on whether the bit is a logic "1" or "0". In each case, the halfway point of the voltage difference is determined by coupling to the midpoint of a pair of resistive components having essentially the same value. The value of the stored voltage represents the analog value of the digital word. The process is preferably repeated for the same word and the two resulting final voltages is averaged to eliminate any effect of a slight difference in component values in a pair.

Abstract: A volume control circuit for a BTSC multi-channel signal includes a trap for the SAP frequency components, a pair of delay lines and a combiner circuit forming a transversal equalizer for shaping a frequency response characteristic that attenuates stereo L+R low frequency components more than L-R mid-frequency components, a pilot frequency trap and a resistance controlled inverting amplifier, all for producing a variable frequency response in a first path. A fixed frequency response, complementary to that at minimum attenuation in the first path, is provided in a second path, the outputs of the two paths being combined to produce an overall frequency response that is variable from unity across the frequency band to a response corresponding to that in the second path.

Abstract: A linear gain differential amplifier having feedback stabilization which is capable of providing inverted and noninverted outputs of equal amplitude is disclosed. A pair of coupled voltage following, feedback stabilized amplifier circuits provide a differential output which is a function of only the respective input signals and the passive component values in the circuit. The present invention is capable of operating at high frequencies over a wide bandwidth and is particularly adapted for video signal processing where linear gain, DC stability, phase compensation and high frequency response are required in order to prevent video luminance and chrominance fluctuations caused by differential gain and phase distortion.

Abstract: A system and method for stabilizing a voltage controlled oscillator (VCO) in an FM modulator is disclosed. The frequencies of a reference carrier and the VCO are sequentially detected in the same frequency discriminator, sampled and stored for later comparison in generating an error signal representing the average frequency difference between these two signals. This error signal is then summed with detected audio information and provided to the VCO as a correction signal for matching the VCO's frequency with the reference frequency of the carrier. VCO signal instabilities due to system drift are thus eliminated for improved signal processing. A time-based switching approach is utilized for sequentially detecting and sampling the reference carrier and the VCO output. One embodiment of the invention utilizes AC coupling in the correction signal feedback loop eliminating DC signal drift and improving system operating stability.

Abstract: A noise processing system is described for use in protecting a television receiver's sync processing path and its video processing path from impulse noise. To protect the video processing path, a first noise canceller receives a composite video signal, detects each noise pulse therein which exceeds a video noise threshold, and replaces each such noise pulse with a selected voltage level. The resultant noise processed video may then be applied to the receiver's video processing path. To protect the sync processing path, another noise canceller receives the composite video signal, detects noise pulses therein which exceed a sync noise threshold, generates a detection pulse for each such noise pulse, and combines the detection pulses with composite video so as to cancel the noise pulses. Thus, another noise processed video signal is developed for application to the receiver's sync processing path.

Abstract: An AFC circuit for a television system having stereophonic sound is disclosed. In response to a channel change, which causes a significant change in the level of the AFC error signal, the error signal is coupled substantially without modification to the local oscillator control terminal and the sound is muted. After an interval sufficient to permit frequency lock to be achieved the error signal is then coupled to the oscillator through a low pass filter and the muting operation is terminated.