Patents by Inventor Victor J. Menasce

Victor J. Menasce has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Cache-memory architecture comprising a single address tag for each cache memory
    Patent number: 5193166
    Abstract: A cache-memory system comprising a processor bus for communicating between an associated processor (CPU) and associated cache-memory management units (CMMUs) communicating through the processor bus and each having a single cache address tag for addressing one associated cache; and each one of the plurality of CMMUs communicating through an associated one of a plurality of memory buses with a main memory of the system.
    Type: Grant
    Filed: April 20, 1992
    Date of Patent: March 9, 1993
    Assignee: Bell-Northern Research Ltd.
    Inventor: Victor J. Menasce