Patents by Inventor Victor J. Wu

Victor J. Wu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240094233
    Abstract: The present invention relates to methods, devices and systems for associating consumable data with an assay consumable used in a biological assay. Provided are assay systems and associated consumables, wherein the assay system adjusts one or more steps of an assay protocol based on consumable data specific for that consumable. Various types of consumable data are described, as well as methods of using such data in the conduct of an assay by an assay system. The present invention also relates to consumables (e.g., kits and reagent containers), software, data deployable bundles, computer-readable media, loading carts, instruments, systems, and methods, for performing automated biological assays.
    Type: Application
    Filed: July 18, 2023
    Publication date: March 21, 2024
    Inventors: Jacob N. WOHLSTADTER, Manish KOCHAR, Peter J. BOSCO, Ian D. CHAMBERLIN, Bandele JEFFREY-COKER, Eric M. JONES, Gary I. KRIVOY, Don E. KRUEGER, Aaron H. LEIMKUEHLER, Pei-Ming WU, Kim-Xuan NGUYEN, Pankaj OBEROI, Louis W. PANG, Jennifer PARKER, Victor PELLICIER, Nicholas SAMMONS, George SIGAL, Michael L. VOCK, Stanley T. SMITH, Carl C. STEVENS, Rodger D. OSBORNE, Kenneth E. PAGE, Michael T. WADE, Jon WILLOUGHBY, Lei WANG, Xinri CONG, Kin NG
  • Patent number: 11501142
    Abstract: A download dispatch circuit initiates download of an input tile of an input feature map in response to a source buffer of two or more source buffers being available for the input tile, and indicates that the input tile is available in response to completion of the download. An operation dispatch circuit initiates a neural network operation on the input tile in response to the input tile being available and a first destination buffer of two or more destination buffers being available for an output tile of an output feature map, and indicates that the output tile is available in response to completion of the neural network operation. An upload dispatch circuit initiates upload of the output tile to the output feature map in response to the output tile being available, and indicates that the first destination buffer is available in response to completion of the upload.
    Type: Grant
    Filed: April 3, 2019
    Date of Patent: November 15, 2022
    Assignee: XILINX, INC.
    Inventors: Victor J. Wu, Poching Sun, Thomas A. Branca, Justin Thant Hsin Oo
  • Patent number: 11194490
    Abstract: A circuit arrangement includes a memory circuit, data upload circuitry, data formatting circuitry, and a systolic array (SA). The data upload circuitry inputs a multi-dimensional data set and stores the multi-dimensional data set in the memory circuit. The data formatting circuitry reads subsets of the multi-dimensional data set from the memory circuit. The data formatting circuitry arranges data elements of the subsets into data streams, and outputs data elements in the data streams in parallel. The SA includes rows and columns of multiply-and-accumulate (MAC) circuits. The SA inputs data elements of the data streams to columns of MAC circuits in parallel, inputs filter values to rows of MAC circuits in parallel, and computes an output feature map from the data streams and the filter values.
    Type: Grant
    Filed: April 18, 2018
    Date of Patent: December 7, 2021
    Assignee: XILINX, INC.
    Inventors: Ravi Sunkavalli, Victor J. Wu, Poching Sun