Abstract: System and method to generate automatically a compact application code suitable for taking advantage of the intrinsic power of processors. The system can generate the application code executable by a processor from a formal specification associated with an application, the formal specification including operators, and the system including an analyzer to code each operator of the formal specification by a corresponding operation code followed by a minimum number of input code(s) and output code identifying input and output parameters associated with the operator, thus automatically generating a compact application code suitable for being stored in a memory associated with the processor and for being executed by an interpreter of the processor.

Abstract: System and method to generate automatically a compact application code suitable for taking advantage of the intrinsic power of processors. The system can generate the application code executable by a processor from a formal specification associated with an application, the formal specification including operators, and the system including an analyzer to code each operator of the formal specification by a corresponding operation code followed by a minimum number of input code(s) and output code identifying input and output parameters associated with the operator, thus automatically generating a compact application code suitable for being stored in a memory associated with the processor and for being executed by an interpreter of the processor.

Abstract: A method and device for loading and executing a plurality of instructions in an avionics system including a processor including at least two cores and a memory controller, each of the cores including a private memory. The plurality of instructions is loaded and executed by execution slots such that, during a first execution slot, a first core has access to the memory controller for transmitting at least one piece of data stored in the private memory thereof and for receiving and storing at least one datum and an instruction from the plurality of instructions in the private memory thereof, while the second core does not have access to the memory controller and executes at least one instruction previously stored in the private memory thereof and such that, during a second execution slot, the roles of the two cores are reversed.

Abstract: A method and device for loading and executing a plurality of instructions in an avionics system including a processor including at least two cores and a memory controller, each of the cores including a private memory. The plurality of instructions is loaded and executed by execution slots such that, during a first execution slot, a first core has access to the memory controller for transmitting at least one piece of data stored in the private memory thereof and for receiving and storing at least one datum and an instruction from the plurality of instructions in the private memory thereof, while the second core does not have access to the memory controller and executes at least one instruction previously stored in the private memory thereof and such that, during a second execution slot, the roles of the two cores are reversed.