Abstract: This disclosure provides a device and method for synchronizing local oscillator (LO) chains. The method can include sampling first I-data and first Q-data to generate first sampled I-data and first sampled Q-data based on a sampling clock signal. The method can also include calibrating the sampling clock signal based on the first sampled I-data and the first sampled Q-data to generate a first calibrated sampling clock signal, the first calibrated sampling clock signal indicating an optimal sample position to sample the first I-data and the first Q-data. The method can also include synchronizing a phase of the first LO chain and a second LO chain based on the first calibrated sampling clock signal.

Abstract: Methods and apparatus for synchronizing dividers in different LO paths using pulse swallowing. One example apparatus generally includes a first path having a first frequency divider configured to generate a first divided signal from a first periodic signal; a second path having a second frequency divider configured to generate a second divided signal from a second periodic signal; a phase detector configured to compare phases of a first sensing signal based on the first divided signal and a second sensing signal based on the second divided signal and to generate a first trigger signal if the first and second sensing signals are out-of-phase; and a first pulse suppressor configured to suppress a pulse of the first periodic signal for at least one cycle in response to the first trigger signal to adjust a phase of the first divided signal.

Abstract: Systems and methods for biasing frequency oscillators to minimize phase noise are disclosed. The system may comprise a tank circuit having an inductor, at least a first coupling capacitor and a second coupling capacitor. The system may further comprise a varactor circuit electrically connected to the first coupling capacitor and the second coupling capacitor. The system may further comprise at least one first metal oxide semiconductor (MOS) device electrically connected in shunt with the tank circuit and a bias voltage. The at least one first MOS device may be electrically connected to a first gate bias voltage configured to bias the at least one first MOS device such that a first gate-to-source voltage of the at least one first MOS device remains below the first threshold voltage.

Abstract: Systems and methods for biasing frequency oscillators to minimize phase noise are disclosed. The system may comprise a tank circuit having an inductor, at least a first coupling capacitor and a second coupling capacitor. The system may further comprise a varactor circuit electrically connected to the first coupling capacitor and the second coupling capacitor. The system may further comprise at least one first metal oxide semiconductor (MOS) device electrically connected in shunt with the tank circuit and a bias voltage. The at least one first MOS device may be electrically connected to a first gate bias voltage configured to bias the at least one first MOS device such that a first gate-to-source voltage of the at least one first MOS device remains below the first threshold voltage.

Abstract: The present invention, in general, provides for a testing system and method for detecting defects within a circuit. A current signature of the quiescent current of the circuit is determined, and certain constant values are calculated based on the current signature using a linear iterative regression. A defect free state for the circuit associated with a minimum quiescent current (IDDQ) is then determined. The IDDQ of the circuit for this state is measured, and a signal indicating the IDDQ at this state is used along with the aforementioned constant values to create upper and lower threshold values. Thereafter, signals indicating the value of IDDQ for a plurality of other states are compared to the upper and lower threshold values. The circuit is determined to be defective if the values of any of the signals is greater than the upper threshold value or is less than the lower threshold value.

Abstract: The present invention, in general, provides for a testing system and method for detecting defects within a circuit. A current signature of the quiescent current of the circuit is determined, and certain constant values are calculated based on the current signature using a linear iterative regression. A defect free state for the circuit associated with a minimum quiescent current (IDDQ) is then determined. The IDDQ of the circuit for this state is measured, and a signal indicating the IDDQ at this state is used along with the aforementioned constant values to create upper and lower threshold values. Thereafter, signals indicating the value of IDDQ for a plurality of other states are compared to the upper and lower threshold values. The circuit is determined to be defective if the values of any of the signals is greater than the upper threshold value or is less than the lower threshold value.