Patents by Inventor Victor K. Eu

Victor K. Eu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 4473939
    Abstract: There is herein described a process for fabricating GaAs FETs with an ion implanted channel layer wherein an ion implanted substrate is capless annealed under an arsine overpressure, and a relatively shallow portion of the outer surface of the substrate in the active layer is removed for the deposition of a gate metallic electrode.
    Type: Grant
    Filed: December 27, 1982
    Date of Patent: October 2, 1984
    Assignee: Hughes Aircraft Company
    Inventors: Milton Feng, Victor K. Eu, Hilda Kanber
  • Patent number: 4407694
    Abstract: Silicon doping of GaAs epitaxial layers grown using the AsCl.sub.3 /H.sub.2 /GaAs:Ga CVD system is accomplished using AsCl.sub.3 :SiCl.sub.4 liquid doping solutions. These solutions can be readily prepared with reproducible compositions and provide excellent doping control. Fine adjustments in the doping level can be achieved by adjusting the H.sub.2 flow rate and by varying the temperature of the doping solution. Doping levels may range from about 5.times.10.sup.15 to 5.times.10.sup.19 cm.sup.-3 by adjusting the mole fraction of SiCl.sub.4 in the doping solution and the H.sub.2 flow rate to change the mole fraction of P.sub.HCl. The epitaxial layers doped using this technique have excellent room temperature and liquid nitrogen mobilities for electron concentrations between 1.times.10.sup.16 cm.sup.-3 and 8.times.10.sup.18 cm.sup.-3. This doping method is particularly useful for the growth of GaAs epitaxial layers for FET devices.
    Type: Grant
    Filed: June 22, 1981
    Date of Patent: October 4, 1983
    Assignee: Hughes Aircraft Company
    Inventors: Victor K. Eu, Milton Feng, Timothy T. Zielinski, James M. Whelan
  • Patent number: 4396437
    Abstract: A post-ion implantation annealing technique is provided to remove implantation damage in the active region of III-V (e.g., GaAs) semiconductor devices formed in a III-V semi-insulating substrate and separated by a field region. The technique involves applying a dielectric encapsulation selectively over the device active area and annealing in a controlled reducing atmosphere which includes the Group V element (e.g., arsenic). The dielectric encapsulant over the active region permits migration of the species employed to render the substrate semi-insulating (e.g., Cr in GaAs substrates), thereby resulting in high carrier mobility in the active region. Without encapsulation, migration of the species in the field region is substantially suppressed, thereby resulting in good inter-device isolation.
    Type: Grant
    Filed: May 4, 1981
    Date of Patent: August 2, 1983
    Assignee: Hughes Aircraft Company
    Inventors: Siang P. Kwok, Milton Feng, Victor K. Eu