Abstract: A computer system is provided wherein a bus master generates a signal indicative of the type of cycle it plans to initiate when requesting bus ownership. Other bus masters may be configured to generate similar cycle-type signals. A bus arbiter samples each master's unique cycle type signal during the request phase, and further receives information regarding the status of various target resources. Based upon the cycle type signals from requesting masters and upon the target resource information, the bus arbiter determines whether a master is planning to access an unavailable target resource. A master that is planning to access an unavailable target resource will be denied access of the bus. Accordingly, other masters intending to initiate cycles to available target resources may be granted ownership of the bus. As a result, target termination retry cycles may be avoided, and bus bandwidth and overall system performance may be improved.

Abstract: A computer system including a host CPU, a primary PCI bus coupled to the CPU, and a bus adapter coupled to the primary PCI bus, wherein the host CPU can access peripherals comprised in the bus adapter even when the bus adapter is inoperable. The bus adapter includes a PCI to PCI interface controller which includes a primary PCI interface for coupling to the primary PCI bus and a secondary PCI interface bridge for coupling to a secondary PCI bus. Peripheral bus interface logic is coupled between the primary PCI interface and the secondary PCI interface, and this interface logic couples to various peripheral devices, including ROM/Flash memory and non-volatile static random access memory (NVSRAM). According to the present invention, a host utility executing on the CPU can access the peripheral devices without having to access the secondary PCI bus.

Abstract: A PCI bus master which determines the termination characteristics of one or more PCI targets coupled to the bus and uses this information to eliminate the wait states that are incurred during a bus cycle when a target device attempts to perform a data phase termination. According to the present invention, at initialization the bus master performs burst cycles on arbitrary address boundaries and stores the target's termination boundaries and cycle conditions. The bus master uses this information during burst transfers to initiate the data phase termination prior to the target, thus preempting the target from performing this termination. This operates to maintain the target's maximum burst capabilities while also eliminating the rearbitration wait states incurred when the bus master receives a termination from the target device. This also allows the bus master to chain together fast back-to-back PCI cycles while retaining bus ownership.

Abstract: A bus system is disclosed which includes first and second buses are coupled via an bus switch. The bus switch may be selectively turned on and off thus allowing the bus system to be electronically configured in a plurality of different configurations.

Abstract: A computer system including a host CPU, a primary PCI bus coupled to the CPU, and a bus adapter coupled to the primary PCI bus, wherein the host CPU can access peripherals comprised in the bus adapter even when the bus adapter is inoperable. The bus adapter includes a PCI to PCI interface controller which includes a primary PCI interface for coupling to the primary PCI bus and a secondary PCI interface bridge for coupling to a secondary PCI bus. Peripheral bus interface logic is coupled between the primary PCI interface and the secondary PCI interface, and this interface logic couples to various peripheral devices, including ROM/Flash memory and non-volatile static random access memory (NVSRAM). According to the present invention, a host utility executing on the CPU can access the peripheral devices without having to access the secondary PCI bus.

Abstract: Apparatus and method for implementing a local proactive hot plug request/acknowledge scheme is disclosed. In a preferred embodiment, each hot pluggable device installable on a computer bus, such as a SCSI bus, is provided with a physical user interface comprising a mechanical request initiator, such as a button or two-position switch, for allowing a user to generate a hot swap request to a controller associated with the bus prior to actual installation of the device on, or removal of the device from, the bus. Upon receipt of the request, the controller determines whether the requested action may be performed, provides a visual indication of its determination to the user via an LED on the user interface and, if installation or removal is determined to be prudent, performs the hot installation/removal in an orderly manner so as not to adversely affect ongoing system operations.

Abstract: A peripheral resource controller such as a caching disk array controller is provided for controlling the transfer of data between a host bus and a peripheral resource, such as an array of hard disk drives. The peripheral resource controller includes a bus interface controller for providing an interface between the host bus and a local bus of the peripheral controller. The bus interface controller further includes a peripheral bus interface which accommodates accesses to a peripheral bus and a DMA controller for controlling direct memory access operations between a local memory of the peripheral controller and a system memory of the host computer. A DMA transfer list memory is coupled to the peripheral bus for storing DMA transfer information. The DMA controller fetches host and local address as well as block size information from the DMA transfer list memory to thereby effectuate DMA operations.

Abstract: A daughter card for mounting to an adapter card, wherein the daughter card includes adapter card connectors for mounting to the adapter card and also an edge connector for insertion directly into a computer slot so that the daughter card may also function as a stand-alone card. The daughter card is both mechanically and electrically compliant as an independent PCI add-in card and includes a PCI edge connector for insertion directly into a PCI slot. This provides additional modularity since the daughter card can be purchased and configured as a separate and independent PCI adapter card as well as for mating to a host adapter card to provide extra functionality to the host adapter card. In addition, since the daughter card can be directly inserted into the PCI bus, the daughter card provides greater component access and probing for testing. Further, the daughter card can be tested independently of the host adapter card during manufacturing functional test, thus providing more reliable testing.

Abstract: Apparatus and method for implementing a local proactive hot plug request/acknowledge scheme is disclosed. In a preferred embodiment, each hot pluggable device installable on a computer bus, such as a SCSI bus, is provided with a physical user interface comprising a mechanical request initiator, such as a button or two-position switch, for allowing a user to generate a hot swap request to a controller associated with the bus prior to actual installation of the device on, or removal of the device from, the bus. Upon receipt of the request, the controller determines whether the requested action may be performed, provides a visual indication of its determination to the user via an LED on the user interface and, if installation or removal is determined to be prudent, performs the hot installation/removal in an orderly manner so as not to adversely affect ongoing system operations.

Abstract: A circuit board is provided having a plurality of vias and uniformly spaced connector stubs arranged upon one or both outer surfaces of the control board. Sets of trace conductors are formed within the control board between the vias. The trace conductors are arranged in two planes within the control board, wherein trace conductors within one plane are laterally offset from trace conductors in the other plane. Laterally offset trace conductors allow close spacing of the trace conductor planes while maximizing the spacing between trace conductors and corresponding reference conductors also placed within the control board. Additionally, the trace conductors are serpentine-shaped when viewed from a perspective perpendicular to the planar surface of the control board.

Abstract: An inexpensive method for fabricating a staggered edge connector for a circuit board. The method is cost effective and includes numerous advantages over the prior art, including allowing more area for signal routing and removing the problems associated with capacitive stubs on edge connector traces associated with prior art designs. The method begins with creating a staggered plurality of blades or fingers. A plating bus is formed on these staggered blades by connecting a gold plating bus to one of the contact pads and then shorting together or connecting the signal lines via a shorting bus. The shorting bus is placed flush with the innermost edge of the edge connector well outside of the actual wipe area of the connectors. The board then undergoes a standard semi-additive process, as well as a final etch and subsequent gold plating. The shorting bar is then drilled out.

Abstract: A sensor circuit for monitoring the operation of a fan in an electronic device includes a current sensor that produces a voltage signal proportional to the magnitude of the current flowing through the fan. The proportional voltage signal is filtered to extract an rms dc signal that then is compared with a minimum and maximum voltage threshold in two voltage comparators. If the voltage of the filtered signal exceeds the maximum threshold value, or is less than the minimum threshold value, a fan failure signal is generated and transmitted to an external monitoring unit. The sensor circuit can be implemented with a standard two-wire fan and interface connector.