Abstract: An IC package includes a leadframe-diepad (112) and a supply-reference comb (114) for interconnecting a die (110) and the package I/O pins (124) in a manner that facilitates substantially ideal EMC performance. The leadframe-diepad includes a diepad-finger (118) and an elongated portion. The leadframe-diepad and the diepad-finger are connected to ground-reference bondpads (128). The supply-reference comb has an elongated spine portion (120) and a finger that is arranged very close to and along the elongated portion of the leadframe-diepad and the diepad-finger respectively for facilitating electromagnetic coupling therebetween and for facilitating local tying of return currents. The supply-reference comb also has a plurality of fingers (116) extending outwardly from the elongated spine portion in a substantially common direction that provides sufficient space in between the fingers for the I/O pins.

Abstract: The present invention relates to a memory array having a plurality of memory cells. In order to combine the compactness of DRAM with the speed and uncomplicated processing profits of SRAM the present invention proposes a memory array having a plurality of memory cells each comprising:—a storage transistor having a drain coupled to a word-line of said array, a source coupled to a bit-line of said array and a gate, and—a control transistor having a drain coupled to the gate of said storage transistor, a source coupled to said bit-line and a gate coupled to said word-line.

Abstract: The present invention relates to a memory array having a plurality of memory cells. In order to combine the compactness of DRAM with the speed and uncomplicated processing profits of SRAM the present invention proposes a memory array having a plurality of memory cells each comprising:—a storage transistor having a drain coupled to a word-line of said array, a source coupled to a bit-line of said array and a gate, and—a control transistor having a drain coupled to the gate of said storage transistor, a source coupled to said bit-line and a gate coupled to said word-line.