Patents by Inventor Victor Key Pecone
Victor Key Pecone has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7437604Abstract: A network storage appliance includes a chassis, enclosing a storage controller and first and second servers. The storage controller has first and second I/O ports for coupling to first and second I/O links. The storage controller controls a plurality of physical disk drives and presents the plurality of physical disk drives as one or more logical disk drives on the first and second I/O links. The servers each have an I/O port for coupling to a respective one of the first and second I/O links. Each of the servers transmits packets to the storage controller over the respective I/O link. The packets include block-level protocol disk commands each identifying one of the logical disk drives, such as SCSI block level protocol commands each identifying one of said logical disk drives as a SCSI logical unit. The I/O links may be FibreChannel, Ethernet, or Infiniband links, for example.Type: GrantFiled: February 10, 2007Date of Patent: October 14, 2008Assignee: Dot Hill Systems CorporationInventors: Ian Robert Davies, George Alexander Kalwitz, Victor Key Pecone
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Publication number: 20080215808Abstract: A write-caching RAID controller includes a CPU that manages transfers of posted-write data from host computers to a volatile memory and transfers of the posted-write data from the volatile memory to a redundant array of storage devices when a main power source is supplying power to the RAID controller. A memory controller transfers the posted-write data received from the host computers to the volatile memory and transfers the posted-write data from the volatile memory for transfer to the redundant array of storage devices as managed by the CPU. The memory controller flushes the posted-write data from the volatile memory to the non-volatile memory when main power fails, during which time capacitors provide power to the memory controller, volatile memory, and non-volatile memory, but not to the CPU, in order to reduce the energy storage requirements of the capacitors.Type: ApplicationFiled: April 16, 2008Publication date: September 4, 2008Applicant: DOT HILL SYSTEMS CORPORATIONInventors: Paul Andrew Ashmore, Dwight Oliver Lintz, Gene Maine, Victor Key Pecone, Rex Weldon Vedder
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Patent number: 7380163Abstract: An apparatus is disclosed for deterministically performing active-active failover of redundant servers in response to a failure of a link on which each server provides a heartbeat to the other server. Each of the servers is configured to take over the identity of the other server on a common network in response to detecting a failure of the other server's link heartbeat. Each server provides a status indicator to a storage controller indicating whether the other server's link heartbeat stopped. The storage controller determines the link has failed if both of the status indicators indicate the other server's heartbeat stopped, and responsively kills one of the servers. The storage controller also receives a heartbeat directly from each server. If only one direct heartbeat stops when the status indicators indicate the link heartbeats stopped, then the storage controller detects one server has failed and inactivates the failed server.Type: GrantFiled: April 23, 2004Date of Patent: May 27, 2008Assignee: Dot Hill Systems CorporationInventors: Ian Robert Davies, George Alexander Kalwitz, Victor Key Pecone
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Patent number: 7334064Abstract: An application server blade for an embedded storage appliance is disclosed. The blade includes a printed circuit board (PCB) with a connector for connecting to a chassis backplane including a local bus. Affixed on the PCB is a server, a portion of a storage controller, and an I/O link coupling the server and storage controller portion. The server transmits packets on the I/O link to the storage controller portion. The packets include commands to transfer data to a storage device controlled by the storage controller. The storage controller portion receives the packets from the server on the I/O link and forwards the commands on the backplane local bus to another portion of the storage controller affixed on a separate PCB also enclosed in the chassis. The blade also includes a removal mechanism for hot-replacement of the blade in the chassis. The blade architecture facilitates software reuse.Type: GrantFiled: April 23, 2004Date of Patent: February 19, 2008Assignee: Dot Hill Systems CorporationInventors: Ian Robert Davies, George Alexander Kalwitz, Victor Key Pecone
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Patent number: 7330999Abstract: A network storage appliance integrates a plurality of servers and a plurality of storage controllers into a single chassis. The storage controllers control transfers of data between the servers and storage devices controlled by the storage controllers. The servers and storage controllers comprise a plurality of field replaceable units (FRUs) that plug into a backplane also enclosed in the chassis. The FRUs are redundant such that any one of the FRUs may fail without incurring loss of availability of the data stored on the storage devices. One of the storage controllers detects a failure of one of the servers and responsively kills the failed server. The failure may be a stopped heartbeat from the failed server. Additionally, one of the storage controllers detects a failure of a heartbeat link coupling the servers and responsively inactivates one of the servers to enable failover to the live server.Type: GrantFiled: April 23, 2004Date of Patent: February 12, 2008Assignee: Dot Hill Systems CorporationInventors: Ian Robert Davies, George Alexander Kalwitz, Victor Key Pecone
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Patent number: 7320083Abstract: An apparatus and method for deterministically killing one of redundant servers on a common network is disclosed. The apparatus includes a chassis that encloses the servers and a storage controller, status indicators generated by the servers to the storage controller, and kill controls, generated by the storage controller to respective ones of the servers, each for killing a respective one of the servers. The status indicators and kill controls are wholly enclosed in the chassis. The kill controls deterministically disable the killed server on the network independently of the state of the server to be killed. That is, the server does not need to be able to respond to a command to be disabled on the network. In one embodiment, the kill controls comprise reset signals. After the storage controller deterministically kills one of the servers, the other server takes over the identity of the killed server on the network.Type: GrantFiled: April 23, 2004Date of Patent: January 15, 2008Assignee: Dot Hill Systems CorporationInventors: Ian Robert Davies, George Alexander Kalwitz, Victor Key Pecone
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Patent number: 7278054Abstract: An apparatus is disclosed for deterministically performing active-active failover of redundant servers in response to a failure of a link on which each server provides a heartbeat to the other server. Each of the servers is configured to take over the identity of the other server on a common network in response to detecting a failure of the other server's link heartbeat. Each server provides a status indicator to a storage controller indicating whether the other server's link heartbeat stopped. The storage controller determines the link has failed if both of the status indicators indicate the other server's heartbeat stopped, and responsively kills one of the servers. The storage controller also receives a heartbeat directly from each server. If only one direct heartbeat stops when the status indicators indicate the link heartbeats stopped, then the storage controller detects one server has failed and inactivates the failed server.Type: GrantFiled: April 23, 2004Date of Patent: October 2, 2007Assignee: Dot Hill Systems CorporationInventors: Ian Robert Davies, George Alexander Kalwitz, Victor Key Pecone
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Patent number: 7146448Abstract: A storage controller configured to adopt orphaned I/O ports is disclosed. The controller includes multiple field-replaceable units (FRUs) that plug into a backplane having local buses. At least two of the FRUs have microprocessors and memory for processing I/O requests received from host computers for accessing storage devices controlled by the controller. Other of the FRUs include I/O ports for receiving the requests from the hosts and bus bridges for bridging the I/O ports to the backplane local buses in such a manner that if one of the processing FRUs fails, the surviving processing FRU detects the failure and responsively adopts the I/O ports previously serviced by the failed FRU to service the subsequently received I/O requests on the adopted I/O ports. The I/O port FRUs also include I/O ports for transferring data with the storage devices that are also adopted by the surviving processing FRU.Type: GrantFiled: September 21, 2004Date of Patent: December 5, 2006Assignee: Dot Hill Systems CorporationInventors: Ian Robert Davies, Gene Maine, Victor Key Pecone
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Patent number: 7062591Abstract: A network storage controller for transferring data between a host computer and a storage device, such as a redundant array of inexpensive disks (RAID), is disclosed. The network storage controller includes at least one channel interface module which is adapted to be connected to the host computer and storage device. The channel interface module is connected to a passive backplane, and selectively transfers data between the host computer and storage device and the passive backplane. The network storage controller also includes at least one controller memory module, attached to the passive backplane. The controller memory module communicates with the channel interface module via the passive backplane, and processes and temporarily stores data received from the host computer or storage device. In applications where redundancy is required, at least two controller memory modules and at least two channel interface modules are used.Type: GrantFiled: September 28, 2001Date of Patent: June 13, 2006Assignee: Dot Hill Systems Corp.Inventor: Victor Key Pecone
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Patent number: 6839788Abstract: A network storage controller for transferring data between a host computer and a storage device, such as a redundant array of inexpensive disks (RAID), described. The network storage controller includes at least one channel interface module which is adapted to be connected to the host computer and storage device. The network storage controller also includes at least one controller memory module, attached to a passive backplane. The controller memory module communicates with the channel interface module. In applications where redundancy is required, at least two controller memory modules and at least two channel interface modules are used. The controller memory modules may mirror data between one another using the passive backplane and a shared communication path on the channel interface modules.Type: GrantFiled: September 28, 2001Date of Patent: January 4, 2005Assignee: Dot Hill Systems Corp.Inventor: Victor Key Pecone
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Publication number: 20030065836Abstract: A network storage controller for transferring data between a host computer and a storage device, such as a redundant array of inexpensive disks (RAID), is disclosed. The network storage controller includes at least one channel interface module which is adapted to be connected to the host computer and storage device. The channel interface module is connected to a passive backplane, and selectively transfers data between the host computer and storage device and the passive backplane. The network storage controller also includes at least one controller memory module, attached to the passive backplane. The controller memory module communicates with the channel interface module via the passive backplane, and processes and temporarily stores data received from the host computer or storage device. In applications where redundancy is required, at least two controller memory modules and at least two channel interface modules are used.Type: ApplicationFiled: September 28, 2001Publication date: April 3, 2003Inventor: Victor Key Pecone
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Publication number: 20030065733Abstract: A network storage controller for transferring data between a host computer and a storage device, such as a redundant array of inexpensive disks (RAID), is disclosed. The network storage controller includes at least one channel interface module which is adapted to be connected to the host computer and storage device. The channel interface module is connected to a passive backplane, and selectively transfers data between the host computer and storage device and the passive backplane. The network storage controller also includes at least one controller memory module, attached to the passive backplane. The controller memory module communicates with the channel interface module via the passive backplane, and processes and temporarily stores data received from the host computer or storage device. In applications where redundancy is required, at least two controller memory modules and at least two channel interface modules are used.Type: ApplicationFiled: September 28, 2001Publication date: April 3, 2003Inventor: Victor Key Pecone
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Publication number: 20030065841Abstract: A network storage controller for transferring data between a host computer and a storage device, such as a redundant array of inexpensive disks (RAID), is disclosed. The network storage controller includes at least one channel interface module which is adapted to be connected to the host computer and storage device. The channel interface module is connected to a passive backplane, and selectively transfers data between the host computer and storage device and the passive backplane. The network storage controller also includes at least one controller memory module, attached to the passive backplane. The controller memory module communicates with the channel interface module via the passive backplane, and processes and temporarily stores data received from the host computer or storage device. In applications where redundancy is required, at least two controller memory modules and at least two channel interface modules are used.Type: ApplicationFiled: September 28, 2001Publication date: April 3, 2003Inventor: Victor Key Pecone
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Patent number: 6477593Abstract: An I/O bridge system comprises a motherboard including first and second busses, e.g., first and second PCI busses. A I/O bridge circuit is connected between the first and second busses and operative to communicate therebetween. A first connector is disposed on a side of the motherboard and has the first bus provided thereat. A second connector is disposed on the side of the motherboard, positioned laterally adjacent the first connector and has the second bus provided thereat. An interconnected stack of daughterboards is disposed on the motherboard and connected to the first and second connectors of the motherboard. A daughterboard of the interconnected stack includes an I/O bridge circuit connected to one of the first bus or the second bus depending on the position of the daughterboard in the interconnected stack. The I/O bridge circuit is operative to communicate between one of the motherboard busses and a communications channel such as a Fibre Channel.Type: GrantFiled: June 11, 1998Date of Patent: November 5, 2002Assignee: Adaptec, Inc.Inventors: Farzad Khosrowpour, Victor Key Pecone
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Patent number: 6263391Abstract: The invention is a modular bus bridge that comprises an I/O controller board, an optional display, and various connectors. The connectors allow a choice of backplane mounting or cable connections. The I/O controller board interconnects bus interfaces and controls the display. The I/O controller board is connected to the display by releasable connectors, so the display may be optionally added or removed. The display allows an end-user to scroll through a menu presented on the display and select from the menu. The I/O controller board is coupled to a backplane connector for backplane mounting. A cable interface can be releasably connected to the backplane connector if cable connections are desired instead of backplane mounting.Type: GrantFiled: September 24, 1998Date of Patent: July 17, 2001Assignee: Adaptec, Inc.Inventors: Victor Key Pecone, Dwayne Howard Swanson, John M. Hartling
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Patent number: 6098140Abstract: The invention is a bus bridge for connecting a computer to peripheral devices over plurality of different bus interface configurations. The bus bridge comprises a motherboard and daughterboards. The daughterboards can be connected to the motherboard or to other daughterboards to create a new bus interface configuration. The bus bridge detects the new bus interface configuration and retrieves operating parameters to implement the new bus interface configuration. In some embodiments of the invention, the bus interface configuration is a fiber channel to the computer, a first small computer system interface to a first group of the peripheral devices, and a second small computer system interface to a second group of the peripheral devices.Type: GrantFiled: June 11, 1998Date of Patent: August 1, 2000Assignee: Adaptec, Inc.Inventors: Victor Key Pecone, Dwayne Howard Swanson
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Patent number: 6044207Abstract: An enhanced performance dual port I/O bus bridge to connect a first I/O bus of bandwidth B and a second like-type I/O bus of bandwidth B with a simultaneously bi-directional data path operating at a bandwidth of at least B and typically at a bandwidth of from 2B to 4B. The enhanced dual port I/O bus bridge includes a first bridge interface and a second bridge interface to a first I/O bus and a second I/O bus respectively. The bridge also includes a first data access path buffering data and having a bandwidth of at least B between the first bridge interface and a data cache, and a second data access path buffering data and having a bandwidth of at least B between the second bridge interface and the same data cache. The data cache can be a RAID type cache. The enhanced I/O bus bridge is operated asynchronously by a means for controlling simultaneous bi-directional data flow between the first bridge interface and the second bridge interface by way of concurrent dual port access to the shared data cache.Type: GrantFiled: March 21, 1997Date of Patent: March 28, 2000Assignee: Adaptec, Inc.Inventors: Victor Key Pecone, Edward Stokes Quicksall
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Patent number: 6012123Abstract: An external I/O controller system between a host system and a Redundant Array of Independent Disks (RAID) array, having a processor complex for coordinating RAID parity write operations to a member disk in a RAID array, and a cache memory complex that asynchronously executes the RAID parity write operation independent of the processor complex and any processor complex resources. The cache memory complex includes a first cache memory and a second cache memory that operate in concert to achieve increased RAID parity write efficiency for a RAID Level 3, 4, 5, or 6 write operation. The I/O controller of the present invention also performs substantially concurrent manipulations on the new host data being written to the RAID array and the old host data and old parity data used to generate a new parity data corresponding to the new host data.Type: GrantFiled: June 10, 1997Date of Patent: January 4, 2000Inventors: Victor Key Pecone, Ian R. Davies
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Patent number: D395881Type: GrantFiled: October 27, 1997Date of Patent: July 7, 1998Assignee: Adaptec, Inc.Inventors: John M. Hartling, Thomas John Lavan, Robert Arthur Hoxsey, Victor Key Pecone, Stanton Michael Manzanares, Randall D. Decker