Patents by Inventor Victor Kitch

Victor Kitch has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7807480
    Abstract: A test cell for localizing defects includes a first active region, a second active region formed substantially parallel to the first active region, a third active region formed substantially parallel to the first and second active regions, a fourth active region formed between the first and second active regions, and a fifth active region formed between the second and third active regions. The fourth and fifth active regions are formed adjacent to opposite end portions of the second active region. The fourth and fifth active regions are also formed substantially perpendicular to the second active region.
    Type: Grant
    Filed: December 14, 2007
    Date of Patent: October 5, 2010
    Assignee: PDF Solutions, Inc.
    Inventors: Brian Stine, Victor Kitch, Mark Zwald, Stefano Tonello
  • Publication number: 20080169466
    Abstract: A test cell for localizing defects includes a first active region, a second active region formed substantially parallel to the first active region, a third active region formed substantially parallel to the first and second active regions, a fourth active region formed between the first and second active regions, and a fifth active region formed between the second and third active regions. The fourth and fifth active regions are formed adjacent to opposite end portions of the second active region. The fourth and fifth active regions are also formed substantially perpendicular to the second active region.
    Type: Application
    Filed: December 14, 2007
    Publication date: July 17, 2008
    Applicant: PDF Solutions, Inc.
    Inventors: Brian Stine, Victor Kitch, Mark Zwald, Stefano Tonello
  • Patent number: 6200900
    Abstract: Capacitance between interconnects lines of a semiconductor device is reduced by providing air voids between the interconnects. The air voids are produced by depositing a dielectric over and partially between the pairs of interconnects and the substrate between them, and etching (preferably by sputter etch) in a controlled and coordinated manner so as to produce air voids in the dielectric between the interconnects. The tops of the air voids are below the level to which the uppermost surfaces of the interconnect is then exposed during subsequent processing so that the air voids remain intact during such subsequent processing.
    Type: Grant
    Filed: October 8, 1999
    Date of Patent: March 13, 2001
    Assignee: National Semiconductor Corporation
    Inventor: Vassili Victor Kitch