Patents by Inventor Victor Ku

Victor Ku has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7655557
    Abstract: The present invention provides a complementary metal oxide semiconductor integration process whereby a plurality of silicided metal gates are fabricated atop a gate dielectric. Each silicided metal gate that is formed using the integration scheme of the present invention has the same silicide metal phase and substantially the same height, regardless of the dimension of the silicide metal gate. The present invention also provides various methods of forming a CMOS structure having silicided contacts in which the polySi gate heights are substantially the same across the entire surface of a semiconductor structure.
    Type: Grant
    Filed: June 24, 2008
    Date of Patent: February 2, 2010
    Assignee: International Business Machines Corporation
    Inventors: Ricky S. Amos, Diane C. Boyd, Cyril Cabral, Jr., Richard D. Kaplan, Jakub T. Kedzierski, Victor Ku, Woo-Hyeong Lee, Ying Li, Anda C. Mocuta, Vijay Narayanan, An L. Steegen, Maheswaren Surendra
  • Patent number: 7635648
    Abstract: A method for fabricating dual material gate structures in a device is provided. The dual material gate structures have different gate electrode materials in different regions of the device. In one embodiment, the method includes providing a substrate having a patterned first gate electrode and a patterned first gate dielectric layer disposed on the substrate, removing a portion of the first gate electrode from the substrate to define a trench on the substrate, and filling the trench to form a second gate electrode.
    Type: Grant
    Filed: April 10, 2008
    Date of Patent: December 22, 2009
    Assignee: Applied Materials, Inc.
    Inventors: Igor Peidous, Victor Ku, Joe Piccirillo
  • Publication number: 20090258484
    Abstract: A method for fabricating dual material gate structures in a device is provided. The dual material gate structures have different gate electrode materials in different regions of the device. In one embodiment, the method includes providing a substrate having a patterned first gate electrode and a patterned first gate dielectric layer disposed on the substrate, removing a portion of the first gate electrode from the substrate to define a trench on the substrate, and filling the trench to form a second gate electrode.
    Type: Application
    Filed: April 10, 2008
    Publication date: October 15, 2009
    Inventors: IGOR PEIDOUS, Victor Ku, Joe Piccirillo
  • Publication number: 20080254622
    Abstract: The present invention provides a complementary metal oxide semiconductor integration process whereby a plurality of silicided metal gates are fabricated atop a gate dielectric. Each silicided metal gate that is formed using the integration scheme of the present invention has the same silicide metal phase and substantially the same height, regardless of the dimension of the silicide metal gate. The present invention also provides various methods of forming a CMOS structure having silicided contacts in which the polySi gate heights are substantially the same across the entire surface of a semiconductor structure.
    Type: Application
    Filed: June 24, 2008
    Publication date: October 16, 2008
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Ricky S. Amos, Diane C. Boyd, Cyril Cabral, Richard D. Kaplan, Jakub T. Kedzierski, Victor Ku, Woo-Hyeong Lee, Ying Li, Anda C. Mocuta, Vijay Narayanan, An L. Steegen, Maheswaren Surendra
  • Patent number: 7411227
    Abstract: The present invention provides a complementary metal oxide semiconductor integration process whereby a plurality of silicided metal gates are fabricated atop a gate dielectric. Each silicided metal gate that is formed using the integration scheme of the present invention has the same silicide metal phase and substantially the same height, regardless of the dimension of the silicide metal gate. The present invention also provides various methods of forming a CMOS structure having silicided contacts in which the polySi gate heights are substantially the same across the entire surface of a semiconductor structure.
    Type: Grant
    Filed: April 19, 2006
    Date of Patent: August 12, 2008
    Assignee: International Business Machines Corporation
    Inventors: Ricky S. Amos, Diane C. Boyd, Cyril Cabral, Jr., Richard D. Kaplan, Jakub T. Kedzierski, Victor Ku, Woo-Hyeong Lee, Ying Li, Anda C. Mocuta, Vijay Narayanan, An L. Steegen, Maheswaren Surendra
  • Patent number: 7326610
    Abstract: Silicide is introduced into the gate region of a CMOS device through different process options for both conventional and replacement gate types processes. Placement of silicide in the gate itself, introduction of the silicide directly in contact with the gate dielectric, introduction of the silicide as a fill on top of a metal gate all ready in place, and introduction the silicide as a capping layer on polysilicon or on the existing metal gate, are presented. Silicide is used as an option to connect between PFET and NFET devices of a CMOS structure. The processes protect the metal gate while allowing for the source and drain silicide to be of a different silicide than the gate silicide. A semiconducting substrate is provided having a gate with a source and a drain region. A gate dielectric layer is deposited on the substrate, along with a metal gate layer. The metal gate layer is then capped with a silicide formed on top of the gate, and conventional formation of the device then proceeds.
    Type: Grant
    Filed: November 10, 2005
    Date of Patent: February 5, 2008
    Assignee: International Business Machines Corporation
    Inventors: Ricky S. Amos, Douglas A. Buchanan, Cyril Cabral, Jr., Evgeni P. Gousev, Victor Ku, An Steegen
  • Publication number: 20070134861
    Abstract: Semiconductor devices and methods of manufacture thereof are disclosed. A preferred embodiment includes providing a workpiece, forming a gate dielectric material over the workpiece, the gate dielectric material comprising an insulator and at least one metal element, and forming a conductive material over the gate dielectric material. The conductive material comprises the at least one metal element of the gate dielectric material.
    Type: Application
    Filed: December 14, 2005
    Publication date: June 14, 2007
    Inventors: Jin-Ping Han, Renee Mo, Tsong Tai, Anita Madan, Nivo Rovedo, Victor Ku, Martin Frank, Daeyoung Lim, Richard Haight
  • Publication number: 20060189061
    Abstract: The present invention provides a complementary metal oxide semiconductor integration process whereby a plurality of silicided metal gates are fabricated atop a gate dielectric. Each silicided metal gate that is formed using the integration scheme of the present invention has the same silicide metal phase and substantially the same height, regardless of the dimension of the silicide metal gate. The present invention also provides various methods of forming a CMOS structure having silicided contacts in which the polySi gate heights are substantially the same across the entire surface of a semiconductor structure.
    Type: Application
    Filed: April 19, 2006
    Publication date: August 24, 2006
    Inventors: Ricky Amos, Diane Boyd, Cyril Cabral, Richard Kaplan, Jakub Kedzierski, Victor Ku, Woo-Hyeong Lee, Ying Li, Anda Mocuta, Vijay Narayanan, An Steegen, Maheswaren Surendra
  • Patent number: 7056782
    Abstract: The present invention provides a complementary metal oxide semiconductor integration process whereby a plurality of silicided metal gates are fabricated atop a gate dielectric. Each silicided metal gate that is formed using the integration scheme of the present invention has the same silicide metal phase and substantially the same height, regardless of the dimension of the silicide metal gate. The present invention also provides various methods of forming a CMOS structure having silicided contacts in which the polySi gate heights are substantially the same across the entire surface of a semiconductor structure.
    Type: Grant
    Filed: February 25, 2004
    Date of Patent: June 6, 2006
    Assignee: International Business Machines Corporation
    Inventors: Ricky S. Amos, Diane C. Boyd, Cyril Cabral, Jr., Richard D. Kaplan, Jakub T. Kedzierski, Victor Ku, Woo-Hyeong Lee, Ying Li, Anda C. Mocuta, Vijay Narayanan, An L. Steegen, Maheswaran Surendra
  • Patent number: 7056794
    Abstract: A method is provided for fabricating a single-metal or dual metal replacement gate structure for a semiconductor device; the structure includes a silicide contact to the gate region. A dummy gate structure and sacrificial gate dielectric are removed to expose a portion of the substrate; a gate dielectric is formed thereon. A metal layer is formed overlying the gate dielectric and the dielectric material. This metal layer may conveniently be a blanket metal layer covering a device wafer. A silicon layer is then formed overlying the metal layer; this layer may also be a blanket wafer. A planarization or etchback process is then performed, so that the top surface of the dielectric material is exposed while other portions of the metal layer and the silicon layer remain in the gate region and have surfaces coplanar with the top surface of the dielectric material. A silicide contact is then formed which is in contact with the metal layer in the gate region.
    Type: Grant
    Filed: January 9, 2004
    Date of Patent: June 6, 2006
    Assignee: International Business Machines Corporation
    Inventors: Victor Ku, An Steegen, Hsing-Jen C. Wann
  • Publication number: 20060105515
    Abstract: Silicide is introduced into the gate region of a CMOS device through different process options for both conventional and replacement gate types processes. Placement of silicide in the gate itself, introduction of the silicide directly in contact with the gate dielectric, introduction of the silicide as a fill on top of a metal gate all ready in place, and introduction the silicide as a capping layer on polysilicon or on the existing metal gate, are presented. Silicide is used as an option to connect between PFET and NFET devices of a CMOS structure. The processes protect the metal gate while allowing for the source and drain silicide to be of a different silicide than the gate silicide. A semiconducting substrate is provided having a gate with a source and a drain region. A gate dielectric layer is deposited on the substrate, along with a metal gate layer. The metal gate layer is then capped with a silicide formed on top of the gate, and conventional formation of the device then proceeds.
    Type: Application
    Filed: November 10, 2005
    Publication date: May 18, 2006
    Inventors: Ricky Amos, Douglas Buchanan, Cyril Cabral, Evgeni Gousev, Victor Ku, An Steegen
  • Patent number: 7041538
    Abstract: A high-performance recessed channel CMOS device including an SOI layer having a recessed channel region and adjoining extension implant regions and optional halo implant regions; and at least one gate region present atop the SOI layer and a method for fabricating the same are provided. The adjoining extension and optional halo implant regions have an abrupt lateral profile and are located beneath said gate region.
    Type: Grant
    Filed: November 14, 2003
    Date of Patent: May 9, 2006
    Assignee: International Business Machines Corporation
    Inventors: Meikei Ieong, Omer H. Dokumaci, Thomas S. Kanarsky, Victor Ku
  • Patent number: 7029966
    Abstract: Silicide is introduced into the gate region of a CMOS device through different process options for both conventional and replacement gate types processes. Placement of silicide in the gate itself, introduction of the silicide directly in contact with the gate dielectric, introduction of the silicide as a fill on top of a metal gate all ready in place, and introduction the silicide as a capping layer on polysilicon or on the existing metal gate, are presented. Silicide is used as an option to connect between PFET and NFET devices of a CMOS structure. The processes protect the metal gate while allowing for the source and drain silicide to be of a different silicide than the gate silicide. A semiconducting substrate is provided having a gate with a source and a drain region. A gate dielectric layer is deposited on the substrate, along with a metal gate layer. The metal gate layer is then capped with a silicide formed on top of the gate, and conventional formation of the device then proceeds.
    Type: Grant
    Filed: September 18, 2003
    Date of Patent: April 18, 2006
    Assignee: International Business Machines Corporation
    Inventors: Ricky S. Amos, Douglas A. Buchanan, Cyril Cabral, Jr., Evgeni P. Gousev, Victor Ku, An Steegen
  • Patent number: 6974736
    Abstract: A method is provided for fabricating a gate structure for a semiconductor device in which the gate structure has an inner spacer. A replacement-gate process is used in which material is removed in a gate region to expose a portion of the substrate; a gate dielectric is formed on the exposed portion of the substrate; and an inner spacer layer is formed overlying the gate dielectric and the dielectric material. A silicon layer is then formed which overlies the inner spacer layer. The structure is then planarized so that portions of the silicon layer and inner spacer layer remain in the gate region. A silicide gate structure is then formed from the silicon; the silicide gate structure is separated from dielectric material surrounding the gate by the inner spacer layer. The semiconductor device may include a first gate region and a second gate region with an interface therebetween, with the inner spacer layer covering the interface.
    Type: Grant
    Filed: January 9, 2004
    Date of Patent: December 13, 2005
    Assignee: International Business Machines Corporation
    Inventors: Victor Ku, An Steegen, Hsing-Jen C. Wann, Keith Kwong Hon Wong
  • Publication number: 20050186747
    Abstract: The present invention provides a complementary metal oxide semiconductor integration process whereby a plurality of silicided metal gates are fabricated atop a gate dielectric. Each silicided metal gate that is formed using the integration scheme of the present invention has the same silicide metal phase and substantially the same height, regardless of the dimension of the silicide metal gate. The present invention also provides various methods of forming a CMOS structure having silicided contacts in which the polySi gate heights are substantially the same across the entire surface of a semiconductor structure.
    Type: Application
    Filed: February 25, 2004
    Publication date: August 25, 2005
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Ricky Amos, Diane Boyd, Cyril Cabral, Richard Kaplan, Jakub Kedzierski, Victor Ku, Woo-Hyeong Lee, Ying Li, Anda Mocuta, Vijay Narayanan, An Steegen, Maheswaran Surendra
  • Patent number: 6927117
    Abstract: A CMOS silicide metal integration scheme that allows for the incorporation of silicide contacts (S/D and gates) and metal silicide gates using a self-aligned process (salicide) as well as one or more lithography steps is provided. The integration scheme of the present invention minimizes the complexity and cost associated with fabricating a CMOS structure containing silicide contacts and silicide gate metals.
    Type: Grant
    Filed: December 2, 2003
    Date of Patent: August 9, 2005
    Assignee: International Business Machines Corporation
    Inventors: Cyril Cabral, Jr., Jakub T. Kedzierski, Victor Ku, Christian Lavoie, Vijay Narayanan, An L. Steegen
  • Patent number: D890000
    Type: Grant
    Filed: December 31, 2018
    Date of Patent: July 14, 2020
    Assignee: FLIR SYSTEMS AB
    Inventors: Xuan Song, Zhenmei Mao, John Huang, Victor Ku
  • Patent number: D891946
    Type: Grant
    Filed: December 31, 2018
    Date of Patent: August 4, 2020
    Assignee: FLIR Systems AB
    Inventors: Xuan Song, Zhenmei Mao, Yuan Lung Li, Victor Ku
  • Patent number: D891947
    Type: Grant
    Filed: December 31, 2018
    Date of Patent: August 4, 2020
    Assignee: FLIR Systems AB
    Inventors: Xuan Song, Zhenmei Mao, Yuan Lung Li, Victor Ku
  • Patent number: D891958
    Type: Grant
    Filed: December 31, 2018
    Date of Patent: August 4, 2020
    Assignee: FLIR Systems AB
    Inventors: Xuan Song, Zhenmei Mao, Hung Yi Lin, Victor Ku