Patents by Inventor Victor Lee

Victor Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250179838
    Abstract: An interlocking anti-tipping cabinet comprises a cabinet body, multiple drawers, which are mounted inside the cabinet body, and a linkage mechanism. An assembling groove vertically elongates and is formed inside the cabinet body. Each of the multiple drawers has a guiding rail and a blocking chunk, which protrude and face the assembling groove. The linkage mechanism is up-and-down moveable, is mounted in the assembling groove, and has multiple wheels respectively corresponding to the multiple drawers. By structural designs of the guiding rail and the blocking chunk of each of the multiple drawers and the linkage mechanism, the interlocking anti-tipping cabinet locks other drawers when one drawer is pulled open. At the same time, an overall structure of the cabinet is simplified, hence effectively decreasing the assembling difficulty and costs of materials and processing.
    Type: Application
    Filed: November 30, 2023
    Publication date: June 5, 2025
    Applicant: HSIN TIEN SHUN CO., LTD.
    Inventor: Victor LEE
  • Publication number: 20250073717
    Abstract: Microfluidic apparatuses, systems, devices and associated fluid manipulation and extraction devices, and methods of using them are presented. The devices may be useful for analysis of clinical, laboratory, chemical, or biological samples. A fluid application and extraction interface device may include a waste reservoir with a fluid trap extending above a waste chamber, an opening through the waste reservoir above the sample inlet, and a transfer conduit extending through the waste reservoir so that fluid may pass from the transfer conduit into the waste reservoir and be trapped within the waste chamber.
    Type: Application
    Filed: November 19, 2024
    Publication date: March 6, 2025
    Inventors: Mais J. JEBRAIL, Alexandra J. CHO, Victor LEE
  • Patent number: 12172164
    Abstract: Microfluidic apparatuses, systems, devices and associated fluid manipulation and extraction devices, and methods of using them are presented. The devices may be useful for analysis of clinical, laboratory, chemical, or biological samples. A fluid application and extraction interface device may include a waste reservoir with a fluid trap extending above a waste chamber, an opening through the waste reservoir above the sample inlet, and a transfer conduit extending through the waste reservoir so that fluid may pass from the transfer conduit into the waste reservoir and be trapped within the waste chamber.
    Type: Grant
    Filed: December 4, 2023
    Date of Patent: December 24, 2024
    Assignee: mirOculus Inc.
    Inventors: Mais J. Jebrail, Alexandra J. Cho, Victor Lee
  • Patent number: 12056107
    Abstract: Systems, methods, and software to manage tags in association with vertices of a graph. In one implementation, a graph management system identifies a request to tag vertices in the graph, wherein the request indicates one or more attributes to qualify for the tag as part of a conditional expression. The graph management system further identifies vertices in the graph with the one or more attributes. Once identified, the graph management system assigns the tag to the vertices wherein the tag comprises an attribute assigned to the identified vertices.
    Type: Grant
    Filed: August 29, 2022
    Date of Patent: August 6, 2024
    Assignee: TigerGraph, Inc.
    Inventors: Mingxi Wu, Victor Lee
  • Publication number: 20240100524
    Abstract: Microfluidic apparatuses, systems, devices and associated fluid manipulation and extraction devices, and methods of using them are presented. The devices may be useful for analysis of clinical, laboratory, chemical, or biological samples. A fluid application and extraction interface device may include a waste reservoir with a fluid trap extending above a waste chamber, an opening through the waste reservoir above the sample inlet, and a transfer conduit extending through the waste reservoir so that fluid may pass from the transfer conduit into the waste reservoir and be trapped within the waste chamber.
    Type: Application
    Filed: December 4, 2023
    Publication date: March 28, 2024
    Inventors: Mais J. JEBRAIL, Alexandra J. CHO, Victor LEE
  • Patent number: 11857969
    Abstract: A digital microfluidics (DMF) device can be used to extract plasma from whole blood and manipulate the extracted plasma. The device can have a plasma separation membrane disposed between a sample inlet and sample outlet that leads into the DMF device. Once the plasma contacts the actuation electrodes of the DMF device, the plasma can be actively extracted from the whole blood sample by actuating the actuation electrodes to pull the plasma through plasma separation membrane.
    Type: Grant
    Filed: August 15, 2022
    Date of Patent: January 2, 2024
    Assignee: mirOculus Inc.
    Inventors: Mais J. Jebrail, Jorge Abraham Soto Moreno, Victor Lee
  • Patent number: 11833516
    Abstract: Digital microfluidic (DMF) apparatuses, systems, devices and associated fluid manipulation and extraction devices, and methods of using them are presented. The devices may be useful for analysis of clinical, laboratory, chemical, or biological samples. A fluid application and extraction interface device may include a waste reservoir with a fluid trap and a transfer conduit extending through the waste reservoir so that fluid may pass from the transfer conduit into the waste reservoir and be trapped within the waste chamber. A transfer conduit may be configured to double back on itself and to hold a fluid sample. A DMF apparatus may be configured to hold and process large sample volumes.
    Type: Grant
    Filed: December 23, 2021
    Date of Patent: December 5, 2023
    Assignee: mirOculus Inc.
    Inventors: Mais J. Jebrail, Alexandra J. Cho, Victor Lee
  • Publication number: 20230067107
    Abstract: Systems, methods, and software to manage tags in association with vertices of a graph. In one implementation, a graph management system identifies a request to tag vertices in the graph, wherein the request indicates one or more attributes to qualify for the tag as part of a conditional expression. The graph management system further identifies vertices in the graph with the one or more attributes. Once identified, the graph management system assigns the tag to the vertices wherein the tag comprises an attribute assigned to the identified vertices.
    Type: Application
    Filed: August 29, 2022
    Publication date: March 2, 2023
    Inventors: Mingxi Wu, Victor Lee
  • Publication number: 20230049633
    Abstract: A digital microfluidics (DMF) device can be used to extract plasma from whole blood and manipulate the extracted plasma. The device can have a plasma separation membrane disposed between a sample inlet and sample outlet that leads into the DMF device. Once the plasma contacts the actuation electrodes of the DMF device, the plasma can be actively extracted from the whole blood sample by actuating the actuation electrodes to pull the plasma through plasma separation membrane.
    Type: Application
    Filed: August 15, 2022
    Publication date: February 16, 2023
    Inventors: Mais J. JEBRAIL, Jorge Abraham SOTO MORENO, Victor LEE
  • Patent number: 11551808
    Abstract: The invention concerns an Interoperability Environment comprising: a core software engine comprising means to collect and transfer electronic data from any number of sources including medical devices, clinical information systems, hospital information systems, a means to apply rules to improve compliance with hospital approved protocols, standards and guidances, a means to update all subsystems using any given parameter when the parameter is updated in the official recognized source of truth for that parameter, a means to populate the CIS with all required patient information, while at the same time maintaining all quality and process control data in a format supporting advanced analytics separate from the CIS data, a means to communicate notifications to any number of remote electronic devices without limitation of platform and comprising a hardware eco system comprising means to collect, translate, store and send electronic data to the core software engine for any electronic source via communication methods
    Type: Grant
    Filed: January 2, 2019
    Date of Patent: January 10, 2023
    Assignee: Talis Clinical LLC
    Inventors: Gary Colister, Bishoy Magdalla, Giuseppe Saracino, William Murphy, Harish Lecamwasam, Victor Lee, Matthew Schumacher, Kevin Gallagher
  • Patent number: 11502696
    Abstract: Embodiments are directed to systems and methods of implementing an analog neural network using a pipelined SRAM architecture (“PISA”) circuitry disposed in on-chip processor memory circuitry. The on-chip processor memory circuitry may include processor last level cache (LLC) circuitry. One or more physical parameters, such as a stored charge or voltage, may be used to permit the generation of an in-memory analog output using a SRAM array. The generation of an in-memory analog output using only word-line and bit-line capabilities beneficially increases the computational density of the PISA circuit without increasing power requirements.
    Type: Grant
    Filed: October 15, 2018
    Date of Patent: November 15, 2022
    Assignee: Intel Corporation
    Inventors: Amrita Mathuriya, Sasikanth Manipatruni, Victor Lee, Huseyin Sumbul, Gregory Chen, Raghavan Kumar, Phil Knag, Ram Krishnamurthy, Ian Young, Abhishek Sharma
  • Patent number: 11416165
    Abstract: The present disclosure is directed to systems and methods of implementing a neural network using in-memory, bit-serial, mathematical operations performed by a pipelined SRAM architecture (bit-serial PISA) circuitry disposed in on-chip processor memory circuitry. The on-chip processor memory circuitry may include processor last level cache (LLC) circuitry. The bit-serial PISA circuitry is coupled to PISA memory circuitry via a relatively high-bandwidth connection to beneficially facilitate the storage and retrieval of layer weights by the bit-serial PISA circuitry during execution. Direct memory access (DMA) circuitry transfers the neural network model and input data from system memory to the bit-serial PISA memory and also transfers output data from the PISA memory circuitry to system memory circuitry.
    Type: Grant
    Filed: October 15, 2018
    Date of Patent: August 16, 2022
    Assignee: Intel Corporation
    Inventors: Amrita Mathuriya, Sasikanth Manipatruni, Victor Lee, Huseyin Sumbul, Gregory Chen, Raghavan Kumar, Phil Knag, Ram Krishnamurthy, Ian Young, Abhishek Sharma
  • Patent number: 11413617
    Abstract: A digital microfluidics (DMF) device can be used to extract plasma from whole blood and manipulate the extracted plasma. The device can have a plasma separation membrane disposed between a sample inlet and sample outlet that leads into the DMF device. Once the plasma contacts the actuation electrodes of the DMF device, the plasma can be actively extracted from the whole blood sample by actuating the actuation electrodes to pull the plasma through plasma separation membrane.
    Type: Grant
    Filed: July 23, 2018
    Date of Patent: August 16, 2022
    Assignee: MIROCULUS INC.
    Inventors: Mais J. Jebrail, Jorge Abraham Soto Moreno, Victor Lee
  • Patent number: 11347994
    Abstract: The present disclosure is directed to systems and methods of bit-serial, in-memory, execution of at least an nth layer of a multi-layer neural network in a first on-chip processor memory circuitry portion contemporaneous with prefetching and storing layer weights associated with the (n+1)st layer of the multi-layer neural network in a second on-chip processor memory circuitry portion. The storage of layer weights in on-chip processor memory circuitry beneficially decreases the time required to transfer the layer weights upon execution of the (n+1)st layer of the multi-layer neural network by the first on-chip processor memory circuitry portion. In addition, the on-chip processor memory circuitry may include a third on-chip processor memory circuitry portion used to store intermediate and/or final input/output values associated with one or more layers included in the multi-layer neural network.
    Type: Grant
    Filed: October 15, 2018
    Date of Patent: May 31, 2022
    Assignee: Intel Corporation
    Inventors: Amrita Mathuriya, Sasikanth Manipatruni, Victor Lee, Huseyin Sumbul, Gregory Chen, Raghavan Kumar, Phil Knag, Ram Krishnamurthy, Ian Young, Abhishek Sharma
  • Publication number: 20220118455
    Abstract: Digital microfluidic (DMF) apparatuses, systems, devices and associated fluid manipulation and extraction devices, and methods of using them are presented. The devices may be useful for analysis of clinical, laboratory, chemical, or biological samples. A fluid application and extraction interface device may include a waste reservoir with a fluid trap and a transfer conduit extending through the waste reservoir so that fluid may pass from the transfer conduit into the waste reservoir and be trapped within the waste chamber. A transfer conduit may be configured to double back on itself and to hold a fluid sample. A DMF apparatus may be configured to hold and process large sample volumes.
    Type: Application
    Filed: December 23, 2021
    Publication date: April 21, 2022
    Inventors: Mais J. JEBRAIL, Alexandra J. CHO, Victor LEE
  • Patent number: 11253860
    Abstract: Digital microfluidic (DMF) apparatuses, systems, devices and associated fluid manipulation and extraction devices, and methods of using them are presented. The devices may be useful for analysis of clinical, laboratory, chemical, or biological samples. A fluid application and extraction interface device may include a waste reservoir with a fluid trap and a transfer conduit extending through the waste reservoir so that fluid may pass from the transfer conduit into the waste reservoir and be trapped within the waste chamber. A transfer conduit may be configured to double back on itself and to hold a fluid sample. A DMF apparatus may be configured to hold and process large sample volumes.
    Type: Grant
    Filed: June 27, 2019
    Date of Patent: February 22, 2022
    Assignee: mirOculus Inc.
    Inventors: Mais J. Jebrail, Alexandra J. Cho, Victor Lee
  • Patent number: 11151046
    Abstract: The present disclosure is directed to systems and methods of implementing a neural network using in-memory mathematical operations performed by pipelined SRAM architecture (PISA) circuitry disposed in on-chip processor memory circuitry. A high-level compiler may be provided to compile data representative of a multi-layer neural network model and one or more neural network data inputs from a first high-level programming language to an intermediate domain-specific language (DSL). A low-level compiler may be provided to compile the representative data from the intermediate DSL to multiple instruction sets in accordance with an instruction set architecture (ISA), such that each of the multiple instruction sets corresponds to a single respective layer of the multi-layer neural network model. Each of the multiple instruction sets may be assigned to a respective SRAM array of the PISA circuitry for in-memory execution.
    Type: Grant
    Filed: July 6, 2020
    Date of Patent: October 19, 2021
    Assignee: Intel Corporation
    Inventors: Amrita Mathuriya, Sasikanth Manipatruni, Victor Lee, Huseyin Sumbul, Gregory Chen, Raghavan Kumar, Phil Knag, Ram Krishnamurthy, Ian Young, Abhishek Sharma
  • Publication number: 20210314621
    Abstract: A method and apparatus for encoding an image. In one embodiment, the method comprises encoding, using a tiled Cohen-Daubechies-Feauveau (CDF) filter, a plurality of tiles of the image, wherein update step results of one tile edge of a first tile of the plurality of tiles are used as inputs to a predict step of an adjacent tile edge.
    Type: Application
    Filed: April 7, 2021
    Publication date: October 7, 2021
    Inventors: Kevin Howard Betts, David Victor Hobbs, Victor Lee, Kevin Mlazgar
  • Patent number: 10855635
    Abstract: An electronic mail (email) message is received at in email transport infrastructure and has a traffic type identifier identifying a traffic type. Function processing logic in the email transport infrastructure conditionally processes the email message based on the traffic type.
    Type: Grant
    Filed: November 14, 2016
    Date of Patent: December 1, 2020
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Krishna Kumar Parthasarathy, Wayne M. Cranston, William J. Whalen, Neelamadhaba Mahapatro, Wilbert De Graaf, Piyush Gupta, Victor Lee, Mingfeng Xiong
  • Patent number: D1003412
    Type: Grant
    Filed: October 29, 2020
    Date of Patent: October 31, 2023
    Assignee: Fortune Industrial (Vietnam) Joint Stock Company
    Inventors: Daniel Lu, Cali Chen, Victor Lee, Fei Chen, Fang Hong