Patents by Inventor Victor Lee Hanson

Victor Lee Hanson has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • SPDIF clock and data recovery with sample rate converter
    Patent number: 8848849
    Abstract: A system and a technique for recovering data from an input data stream without synchronization of an input sampling circuit to the input data stream determines a count of incoming samples (or frames) without generating a signal that is frequency-locked to the input data stream. A first clock is generated comprising a frequency that is greater than or equal to an expected frequency of the input data stream. A sample count is incremented in response to a sample received in the input data stream, and is decremented in response to a second clock signal. The second clock is generated the first clock signal by passing the first clock signal if the sample count of the sample counter does not equal a predetermined sample count value and by blocking the first clock signal if the sample count equals the predetermined sample count value.
    Type: Grant
    Filed: March 13, 2013
    Date of Patent: September 30, 2014
    Assignee: Avnera Corporation
    Inventors: Samuel J. Peters, Eric P. Etheridge, Victor Lee Hanson, Alexander C. Stange
  • SPDIF Clock and Data Recovery With Sample Rate Converter
    Publication number: 20140270028
    Abstract: A system and a technique for recovering data from an input data stream without synchronization of an input sampling circuit to the input data stream determines a count of incoming samples (or frames) without generating a signal that is frequency-locked to the input data stream. A first clock is generated comprising a frequency that is greater than or equal to an expected frequency of the input data stream. A sample count is incremented in response to a sample received in the input data stream, and is decremented in response to a second clock signal. The second clock is generated the first clock signal by passing the first clock signal if the sample count of the sample counter does not equal a predetermined sample count value and by blocking the first clock signal if the sample count equals the predetermined sample count value.
    Type: Application
    Filed: March 13, 2013
    Publication date: September 18, 2014
    Applicant: Avnera Corporation
    Inventors: Samuel J. Peters, II, Eric P. Etheridge, Victor Lee Hanson, Alexander C. Stange