Abstract: A decoder is provided which does not require the use of a retiming circuit. The decoder operates with an AMI signal, and operates to detect a transition occurring at the center of a bit cell to blank out those transitions which do not coincide with the encoding clock. The decision is made by examining the time between received transitions. Once this is accomplished, an asynchronous logic circuit with two states of memory can be used to structure the decoded AMI data into a NRZ or other format by storing the transitions which occur in the middle of the previous bit cell and outputting a first binary value during the following bit cell for a transition, or if no transitions have occurred in the middle of the previous bit cell, a second binary value is outputted during the following bit period.