Abstract: The exemplary embodiment is for an architecture integrated in a generic System on Chip (SoC) and consisting of reconfigurable coprocessors for executing nested program loops performed in a functional unit array in parallel. The data arrays are accessed from one or more system inputs and from an embedded memory array in parallel. The processed data arrays are sent back to the memory array or to system outputs and enable the acceleration of nested loops. The coprocessors are connected either synchronously or using asynchronous first in first out memories (FIFOs), forming a globally asynchronous locally synchronous system and each coprocessor can be programmed by tagging and rewriting the nested loops in the original program and produces a coprocessor configuration per each nested loop group, which is replaced in the original code with coprocessor input/output operations and control.

Abstract: The proposed architecture is integrated in a generic System on Chip (SoC) and can include or consist of an expanded network interface and an infrastructure for accessing Intellectual Property (IP) cores in the system. The architecture enables the system on chip to communicate with a user workstation connected to a communication network. The invention can be used as a simplified network interface for data exchange, which does not require embedded processors and respective software. The invention can be used to temporarily replace the normal data input and output of an IP core with stimuli and responses used for a variety of purposes.

Abstract: The architectures derived from the proposed template are integrated in a generic System on Chip (SoC) and consist of reconfigurable coprocessors for executing nested program loops whose bodies are expressions of operations performed in a functional unit array in parallel. The data arrays are accessed from one or more system inputs and from an embedded memory array in parallel. The processed data arrays are sent back to the memory array or to system outputs. The architectures enable the acceleration of nested loops compared to execution on a standard processor, where only one operation or datum access can be performed at a time. The invention can be used in a number of applications especially those which involve digital signal processing, such as multimedia and communications. The architectures are used preferably in conjunction with von Neumann processors which are better at implementing control flow.

Abstract: The proposed architecture is integrated in a generic System on Chip (SoC) and can include or consist of an expanded network interface and an infrastructure for accessing Intellectual Property (IP) cores in the system. The architecture enables the system on chip to communicate with a user workstation connected to a communication network. The invention can be used as a simplified network interface for data exchange, which does not require embedded processors and respective software. The invention can be used to temporarily replace the normal data input and output of an IP core with stimuli and responses used for a variety of purposes.