Patents by Inventor Victor Maruri

Victor Maruri has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20030071654
    Abstract: A programmable logic device has many regions of programmable logic, together with relatively general-purpose, programmable, interconnection resources that can be used to make interconnections between virtually any of the logic regions. In addition, various types of more local interconnection resources are associated with each logic region for facilitating the making of interconnections between adjacent or nearby logic regions without the need to use the general-purpose interconnection resources for those interconnections. The local interconnection resources support flexible clustering of logic regions via relatively direct and therefore high-speed interconnections, preferably in both horizontal and vertical directions in the typically two-dimensional array of logic regions. The logic region clustering options provided by the local interconnection resources are preferably boundary-less or substantially boundary-less within the array of logic regions.
    Type: Application
    Filed: November 18, 2002
    Publication date: April 17, 2003
    Inventors: James Schleicher, Jim Park, Sergey Shumarayev, Bruce Pedersen, Tony Ngai, Wei-Jen Huang, Victor Maruri, Rakesh Patel
  • Patent number: 6525564
    Abstract: A programmable logic device has many regions of programmable logic, together with relatively general-purpose, programmable, interconnection resources that can be used to make interconnections between virtually any of the logic regions. In addition, various types of more local interconnection resources are associated with each logic region for facilitating the making of interconnections between adjacent or nearby logic regions without the need to use the general-purpose interconnection resources for those interconnections. The local interconnection resources support flexible clustering of logic regions via relatively direct and therefore high-speed interconnections, preferably in both horizontal and vertical directions in the typically two-dimensional array of logic regions. The logic region clustering options provided by the local interconnection resources are preferably boundary-less or substantially boundary-less within the array of logic regions.
    Type: Grant
    Filed: December 14, 2001
    Date of Patent: February 25, 2003
    Assignee: Altera Corporation
    Inventors: James Schleicher, James Park, Sergey Shumarayev, Bruce Pedersen, Tony Ngai, Wei-Jen Huang, Victor Maruri, Rakesh Patel
  • Patent number: 6407576
    Abstract: A programmable logic integrated circuit device has a plurality of regions of programmable logic disposed on the device in a plurality of intersecting rows and columns of such regions. Interconnection resources (e.g., interconnection conductors, signal buffers/drivers, programmable connectors, etc.) are provided on the device for making programmable interconnections to, from, and/or between the regions. At least some of these interconnection resources are provided in two forms that are architecturally similar (e.g., with similar and substantially parallel routing) but that have significantly different signal propagation speed characteristics. For example, a major or larger portion of such dual-form interconnection resources may have what may be termed normal signal speed, while a smaller minor portion may have significantly faster signal speed. Secondary (e.g.
    Type: Grant
    Filed: March 2, 2000
    Date of Patent: June 18, 2002
    Assignee: Altera Corporation
    Inventors: Tony Ngai, Bruce Pedersen, Sergey Shumarayev, James Schleicher, Wei-Jen Huang, Michael Hutton, Victor Maruri, Rakesh Patel, Peter J. Kazarian, Andrew Leaver, David W. Mendel, Jim Park
  • Publication number: 20020057103
    Abstract: A programmable logic integrated circuit device has a plurality of regions of programmable logic disposed on the device in a plurality of intersecting rows and columns of such regions. Interconnection resources (e.g., interconnection conductors, signal buffers/drivers, programmable connectors, etc.) are provided on the device for making programmable interconnections to, from, and/or between the regions. At least some of these interconnection resources are provided in two forms that are architecturally similar (e.g., with similar and substantially parallel routing) but that have significantly different signal propagation speed characteristics. For example, a major or larger portion of such dual-form interconnection resources may have what may be termed normal signal speed, while a smaller minor portion may have significantly faster signal speed. Secondary (e.g.
    Type: Application
    Filed: January 14, 2002
    Publication date: May 16, 2002
    Applicant: Altera Corporation.
    Inventors: Tony Ngai, Bruce Pedersen, Sergey Shumarayev, James Schleicher, Wei-Jen Huang, Victor Maruri, Rakesh Patel
  • Publication number: 20020041192
    Abstract: A programmable logic device has many regions of programmable logic, together with relatively general-purpose, programmable, interconnection resources that can be used to make interconnections between virtually any of the logic regions. In addition, various types of more local interconnection resources are associated with each logic region for facilitating the making of interconnections between adjacent or nearby logic regions without the need to use the general-purpose interconnection resources for those interconnections. The local interconnection resources support flexible clustering of logic regions via relatively direct and therefore high-speed interconnections, preferably in both horizontal and vertical directions in the typically two-dimensional array of logic regions. The logic region clustering options provided by the local interconnection resources are preferably boundary-less or substantially boundary-less within the array of logic regions.
    Type: Application
    Filed: December 14, 2001
    Publication date: April 11, 2002
    Applicant: Altera Corporation
    Inventors: James Schleicher, Jim Park, Sergey Shumarayev, Bruce Pedersen, Tony Ngai, Wei-Jen Huang, Victor Maruri, Rakesh Patel
  • Patent number: 6366120
    Abstract: A programmable logic device has many regions of programmable logic, together with relatively general-purpose, programmable, interconnection resources that can be used to make interconnections between virtually any of the logic regions. In addition, various types of more local interconnection resources are associated with each logic region for facilitating the making of interconnections between adjacent or nearby logic regions without the need to use the general-purpose interconnection resources for those interconnections. The local interconnection resources support flexible clustering of logic regions via relatively direct and therefore high-speed interconnections, preferably in both horizontal and vertical directions in the typically two-dimensional array of logic regions. The logic region clustering options provided by the local interconnection resources are preferably boundary-less or substantially boundary-less within the array of logic regions.
    Type: Grant
    Filed: March 2, 2000
    Date of Patent: April 2, 2002
    Assignee: Altera Corporation
    Inventors: James Schleicher, James Park, Sergey Shumarayev, Bruce Pedersen, Tony Ngai, Wei-Jen Huang, Victor Maruri, Rakesh Patel