Abstract: A memory request arbitrator is provided for selecting one of a plurality of requesting devices, such as microprocessors, which may make a request to access a memory device common to the plurality of requestors. Requests from the devices are applied in common as a portion of an address to a read only memory, a priority sequencer providing another portion of the address. The read only memory provides a selection signal to the selected requestor. The priority sequencer is periodically updated to thereby change the priority of requestors such that priority is given to each of the requestors over time. The priority sequencer may be temporarily disabled to thereby allow a requestor a "back-to-back" memory access for a multi-cycle memory instruction. Finally, the initial state of the request lines is checked upon system start up to determine whether any of the request lines are unused. Only those request lines associated with presently operating requestors are able to provide request signals to the read only memory.