Patents by Inventor Victor Menasce

Victor Menasce has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7350012
    Abstract: A configurable switching fabric port is disclosed having, in a particular configuration. A first interface that employs port interface resources and leaves at least one interface resource dormant and a second interface utilizing the dormant resource. One particular fault non-tolerant architecture, the RapidIO System, is specifically addressed. One implementation of this system incorporates transmission and reception ports configurable as 16 and 8 bit interfaces. In the 8-bit configuration, an 8-bit interface incorporates the least significant 8-bits of signal resources. Further, in the reduced, or 8-bit configuration, the most significant port interface resources of the 16 bit port are surplus.
    Type: Grant
    Filed: July 9, 2003
    Date of Patent: March 25, 2008
    Assignee: Tundra Semiconductor Corporation
    Inventors: Victor Menasce, Stephane Gagnon
  • Publication number: 20060190641
    Abstract: A buffer management system for cooperating with a packet based switching system is proposed. The purpose of this system is to reduce traffic congestion, ameliorate its effects, provide fairness to each data source, and to increase functionality while respecting advantageous system characteristics. Fabric output buffers include an arbitration function, a quality of service function, and are associated with individual routing tables. The system uses shallow logic that allows for single clock cycle operation even at high clock speeds. In order to provide for system control of bandwidth, sources with bandwidth practices counter to system interests are addressed. Where there is a conflict of sources over a resource, the buffer management system arbitrates traffic to resolve conflicts in a timely manner while fairly allocating traffic share using a weighted round robin arbitration scheme.
    Type: Application
    Filed: April 10, 2006
    Publication date: August 24, 2006
    Inventors: Stephen Routliffe, Huaiqi Xu, Barry Wood, Victor Menasce
  • Patent number: 7076587
    Abstract: A buffer management system for cooperating with a packet based switching system is proposed. The purpose of this system is to reduce traffic congestion, ameliorate its effects, provide fairness to each data source, and to increase functionality while respecting advantageous system characteristics. Fabric output buffers include an arbitration function, a quality of service function, and are associated with individual routing tables. The system uses shallow logic that allows for single clock cycle operation even at high clock speeds. In order to provide for system control of bandwidth, sources with bandwidth practices counter to system interests are addressed. Where there is a conflict of sources over a resource, the buffer management system arbitrates traffic to resolve conflicts in a timely manner while fairly allocating traffic share using a weighted round robin arbitration scheme.
    Type: Grant
    Filed: May 16, 2003
    Date of Patent: July 11, 2006
    Assignee: Tundra Semiconductor Corporation
    Inventors: Stephen Routliffe, Huaiqi Xu, Barry Wood, Victor Menasce
  • Publication number: 20040059957
    Abstract: A configurable switching fabric port is disclosed having, in a particular configuration. A first interface that employs port interface resources and leaves at least one interface resource dormant and a second interface utilizing the dormant resource. One particular fault non-tolerant architecture, the RapidIO System, is specifically addressed. One implementation of this system incorporates transmission and reception ports configurable as 16 and 8 bit interfaces. In the 8-bit configuration, an 8-bit interface incorporates the least significant 8-bits of signal resources. Further, in the reduced, or 8-bit configuration, the most significant port interface resources of the 16 bit port are surplus.
    Type: Application
    Filed: July 9, 2003
    Publication date: March 25, 2004
    Applicant: Tundra Semiconductor Corporation
    Inventors: Victor Menasce, Stephane Gagnon
  • Publication number: 20040044810
    Abstract: A buffer management system for cooperating with a packet based switching system is proposed. The purpose of this system is to reduce traffic congestion, ameliorate its effects, provide fairness to each data source, and to increase functionality while respecting advantageous system characteristics. Fabric output buffers include an arbitration function, a quality of service function, and are associated with individual routing tables. The system uses shallow logic that allows for single clock cycle operation even at high clock speeds. In order to provide for system control of bandwidth, sources with bandwidth practices counter to system interests are addressed. Where there is a conflict of sources over a resource, the buffer management system arbitrates traffic to resolve conflicts in a timely manner while fairly allocating traffic share using a weighted round robin arbitration scheme.
    Type: Application
    Filed: May 16, 2003
    Publication date: March 4, 2004
    Applicant: Tundra Semiconductor Corporation
    Inventors: Stephen Routliffe, Huaiqi Xu, Barry Wood, Victor Menasce