Abstract: An image resynthesis system, a system for training a gap filling module to be used in the image resynthesis system, an image resynthesis method, a computer program product, and a computer-readable medium are provided. The image resynthesis system comprises a source image input module, a forward warping module predicting, for each source image pixel of a source image, a corresponding position in a target image, and predicting a forward warping field which is aligned with the source image, and a gap filling module filling in gaps resulting from application of the forward warping module.

Abstract: The disclosure provides a method for generating relightable 3D portrait using a deep neural network and a computing device implementing the method. A possibility of obtaining, in real time and on computing devices having limited processing resources, realistically relighted 3D portraits having quality higher or at least comparable to quality achieved by prior art solutions, but without utilizing complex and costly equipment is provided.

Abstract: The present invention relates to variant CRISPR nuclease polypeptides, methods of preparing the variant CRISPR nuclease polypeptides, processes for characterizing the variant CRISPR nuclease polypeptides, compositions and cells comprising the variant CRISPR nuclease polypeptides, and methods of using the variant CRISPR nuclease polypeptides. The invention further relates to complexes comprising a variant CRISPR nuclease polypeptide, methods of producing the complexes, processes for characterizing the complexes, cells comprising the complexes, and methods of using the complexes.

Abstract: Synchronizer circuits having controllable metastability are provided, one of which includes: a first flip-flop circuit comprising a first master latch connected in series with a first slave latch; and a second flip-flop circuit comprising a second master latch connected in series with a second slave latch, wherein an output of the first flip-flop circuit is connected to an input of the second flip-flop circuit, at least a portion of the first flip-flop circuit is implemented in a first PWell isolated by an underlying a deep isolation NWell, at least a portion of the first flip-flop circuit is implemented in a first NWell that electrically contacts the deep isolation NWell, the first NWell is connected to a first bias voltage that is less than a positive power supply voltage, and the first PWell is connected to a second bias voltage that is greater than a negative power supply voltage.

Abstract: Synchronizer circuits having controllable metastability are provided, one of which includes: a first flip-flop circuit comprising a first master latch connected in series with a first slave latch; and a second flip-flop circuit comprising a second master latch connected in series with a second slave latch, wherein an output of the first flip-flop circuit is connected to an input of the second flip-flop circuit, at least a portion of the first flip-flop circuit is implemented in a first PWell isolated by an underlying a deep isolation NWell, at least a portion of the first flip-flop circuit is implemented in a first NWell that electrically contacts the deep isolation NWell, the first NWell is connected to a first bias voltage that is less than a positive power supply voltage, and the first PWell is connected to a second bias voltage that is greater than a negative power supply voltage.

Abstract: An electronic device includes a logic circuit, a pullup acceleration circuit, a first signal propagation path, and a second signal propagation path. The first signal propagation path propagates a logic value transition from an input terminal of the logic circuit to an output terminal of the logic circuit through the input terminal, two inverters of the logic circuit, a switch of the logic circuit, and the output terminal within a first amount of time based on a transition at the first input terminal. The second signal propagation path propagates the logic value transition from the input terminal to the output terminal through one inverter of the logic circuit and the pullup acceleration circuit within a second amount of time. The second amount of time is shorter than the first amount of time in response to the logic circuit being non-monotonic with respect to the logic value.

Abstract: An electronic device includes a logic circuit, a pullup acceleration circuit, a first signal propagation path, and a second signal propagation path. The first signal propagation path propagates a logic value transition from an input terminal of the logic circuit to an output terminal of the logic circuit through the input terminal, two inverters of the logic circuit, a switch of the logic circuit, and the output terminal within a first amount of time based on a transition at the first input terminal. The second signal propagation path propagates the logic value transition from the input terminal to the output terminal through one inverter of the logic circuit and the pullup acceleration circuit within a second amount of time. The second amount of time is shorter than the first amount of time in response to the logic circuit being non-monotonic with respect to the logic value.

Abstract: This invention relates to medicine, more specifically, to the surgical treatment of intestinal obstructions using the minimum invasive (endoscopic) method. The invention provides the possibility of the surgical treatment of intestinal obstructions along the entire length of the intestine by means of stenting. The technical result achieved by the first and second subjects of the invention is providing the total surgical treatment of intestinal obstructions in the narrow and large intestine by installing a stent at an intestine obstruction location in a manner allowing further moving the stent during its positioning or removal and avoiding damage to the intestine as a result of the surgical manipulations. Said technical objective is achieved with the first subject of the invention, i.e. the method, as follows.

Abstract: Multi-bit data flip-flops are disclosed that provide bit initialization through propagation of scan bits. Input multiplexers are configured to select between input data bits and input scan bits based upon mode select signals. Master latches receive and latch outputs from the input multiplexers. Slave latches receive and latch outputs from the master latches and also provide propagated input scan bits to the input multiplexers. A first state for the mode select signals selects the input data bits for a data mode of operation, and a second state for the mode select signals selects the input scan bits for a scan mode of operation. Further, the input multiplexers, master latches, and slave latches are configured to operate in an initialization mode to pass a fixed input scan bit through the multi-bit data flip-flop based upon initialization signals (e.g., set and/or reset signals).

Abstract: Multi-bit data flip-flops are disclosed that provide bit initialization through propagation of scan bits. Input multiplexers are configured to select between input data bits and input scan bits based upon mode select signals. Master latches receive and latch outputs from the input multiplexers. Slave latches receive and latch outputs from the master latches and also provide propagated input scan bits to the input multiplexers. A first state for the mode select signals selects the input data bits for a data mode of operation, and a second state for the mode select signals selects the input scan bits for a scan mode of operation. Further, the input multiplexers, master latches, and slave latches are configured to operate in an initialization mode to pass a fixed input scan bit through the multi-bit data flip-flop based upon initialization signals (e.g., set and/or reset signals).

Abstract: A flip-flop structure comprising a master latch and a slave latch. An output of an input stage of the master latch is coupled to the output of the master latch. The input stage is arranged to drive a logical state at the output of the master latch corresponding to a logical state of the received data input signal during a first phase of a clock signal. A feedback component is arranged to sample a logical state at the output of the master latch and to drive a logical state at the output of the master latch based on the sampled logical state at the output of the master latch such that the sampled logical state is maintained, during a second phase of the clock signal.

Abstract: A multi-bit flip-flop includes at least two storage stages. Each of the storage stages includes redundant latches to suppress state corruptions resulting from soft error upset at the storage stage. In addition, the multi-bit flip-flop includes a split clock path that routes different shared clock signals that control the timing of the latches. The shared split clock path reduces or eliminates the impact of soft errors on the clock signals, thereby further limiting the impact of such errors on data stored at the flip-flop. In particular, the split clock path can be distributed over disparate cells in a layout of multi-bit flip-flop, thereby reducing the likelihood that a transient charge will cause a soft error in all paths of the split clock path.

Abstract: A multi-bit flip-flop includes at least two storage stages. Each of the storage stages includes redundant latches to suppress state corruptions resulting from soft error upset at the storage stage. In addition, the multi-bit flip-flop includes a split clock path that routes different shared clock signals that control the timing of the latches. The shared split clock path reduces or eliminates the impact of soft errors on the clock signals, thereby further limiting the impact of such errors on data stored at the flip-flop. In particular, the split clock path can be distributed over disparate cells in a layout of multi-bit flip-flop, thereby reducing the likelihood that a transient charge will cause a soft error in all paths of the split clock path.

Abstract: A flip-flop structure comprising a master latch and a slave latch. An output of an input stage of the master latch is coupled to the output of the master latch. The input stage is arranged to drive a logical state at the output of the master latch corresponding to a logical state of the received data input signal during a first phase of a clock signal. A feedback component is arranged to sample a logical state at the output of the master latch and to drive a logical state at the output of the master latch based on the sampled logical state at the output of the master latch such that the sampled logical state is maintained, during a second phase of the clock signal.

Abstract: An organosiloxane block copolymer having the formula depicted (I) depicted below: ##STR1## wherein: m has a value of 8.0-18.0;n has a value of 1.0-5.0;x has a value of about 0.2 to about 0.7;y has a value of 1 minus the value of x;R is ##STR2## R.sup.1 ##STR3## R.sup.2 is a C.sub.1 -C.sub.5 lower alkylene group; V is a vinyl group; andMe is a methyl group.Preparation of the organosiloxane block copolymer of the above formula (I) by polymerizing .alpha.,w-bis(oxymethyl)polydimethyl-methylvinylsiloxane, and diphenylmethanediisocyanate, and di(oxyethyl)m-toluidine in the presence of a solvent and a catalyst. A composite membrane, which may be used in a pervaporation process, comprising a hydrophilic asymmetric membrane coated with a mixture of an organosiloxane block copolymer, a linking reagent and a catalytically effective amount of a hydrosilylation catalyst.