Abstract: The described method may include receiving user input indicating a configuration identifying a large language model (LLM) and a subset of documents indicated in the configuration as being available to a tenant. The method may include generating one or more vectorizations of content of the subset of documents. The method may include receiving a request to generate a generative response. The method may include generating the generative artificial intelligence (AI) prompt using the content to ground the generative AI prompt. The subset of documents may be identified based on a comparison between a vectorization of the request and the one or more vectorizations and based at least in part on a determination that a user associated with the tenant is permitted to access the subset of documents. The method may include presenting a response to the generative AI prompt, the response generated by the LLM using the generative AI prompt.

Abstract: An apparatus may include a first inverter, a second inverter, a first access transistor, and a second access transistor. The first inverter and a second inverter may be cross-coupled between a first node and a second node to store a signal state represented by voltage values at the first node and the second node. The first and second inverters may be configured to operate reliably under voltage conditions higher than a positive supply voltage of the apparatus. The first access transistor may selectively couple the first node to a bit line, and allow direct control of the first node during access operations. The second access transistor may selectively couple the second node to the bit line, and allow direct control of the second node during access operations. The respective positive supply inputs of the first inverter and the second inverter may be to couple to a voltage supply associated with a higher voltage level than the positive supply voltage of the apparatus.

Abstract: A ReRAM memory array includes ReRAM memory cells and a select circuit having first and second series-connected select transistors connected in series with a ReRAM device. When ReRAM memory cell(s) are selected for programming, the bit line coupled to the ReRAM memory cell(s) to be programmed is biased at a first voltage potential and the source line coupled to the ReRAM memory cell(s) to be programmed is biased at a second voltage potential less than the first voltage potential, the difference between the first voltage potential and the second voltage potential being sufficient to program the ReRAM device. The gates of first and second series-connected select transistors of ReRAM memory cell(s) to be programmed are supplied with positive voltage pulses. The gates of second series-connected select transistors of respective ReRAM memory cell(s) unselected for programming are supplied with a voltage potential insufficient to turn them on.

Abstract: The disclosed exemplary embodiments include computer-implemented systems, apparatuses, and processes that dynamically manage consent, permissioning, and trust between computing systems and unrelated, third-party applications operating within a computing environment. By way of example, the apparatus may receive a request for an element of data that includes an access token and first credential data associated with an application program. When the first credential data corresponds to second credential data associated with the application program, may determine that the requested data element is accessible to the application program and perform operations that validate the access token. Further, and based on the validation of the access token, that apparatus may obtain and encrypt the requested data element, and may transmit the encrypted data element to a device via the communications interface.

Abstract: A ReRAM memory array includes ReRAM memory cells having two series-connected select transistors connected in series with a ReRAM device. When ReRAM memory cell(s) are selected for erasing, the bit line coupled to the ReRAM memory cell(s) to be erased is biased at a first voltage potential. The source line coupled to the ReRAM memory cell(s) to be erased is biased at a second voltage potential greater than the first voltage potential, the difference between the first voltage potential and the second voltage potential being sufficient to erase the ReRAM device. The gates of the series-connected select transistors of the ReRAM memory cell(s) to be erased are supplied with positive voltage pulses. The gates of the series-connected select transistors of the ReRAM memory cell(s) unselected for erasing are supplied with a voltage potential insufficient to turn them on.

Abstract: An apparatus may include a first inverter and a second inverter cross-coupled between a first node and a second node to store a signal state represented by complementary voltages at the first node and the second node. The apparatus may further include a first path defined by the second inverter that includes an impedance element to resist a flow of charge suitable to change the signal state. The apparatus may further include the first inverter and a third inverter selectively cross-coupled between the first node and the second node to store a received signal state represented by the complementary voltages at the first node and the second node responsive to an assertion of a write enable signal.

Abstract: A method of staging a listed property for a real-estate showing including: receiving authorization information to access and control one or more internet of things (IoT) connected devices at the listed property from a first person via a first computer application accessed through a seller computing device; receiving showing settings and timing settings for each of the one or more IoT connected devices; and adjusting each of one or more IoT connected devices for the real-estate showing in accordance with the showing settings and the timing settings.

Abstract: An apparatus may include a first inverter and a second inverter cross-coupled between a first node and a second node to store a signal state represented by complementary voltages at the first node and the second node. The apparatus may further include a first path defined by the second inverter that includes an impedance element to resist a flow of charge suitable to change the signal state. The apparatus may further include the first inverter and a third inverter selectively cross-coupled between the first node and the second node to store a received signal state represented by the complementary voltages at the first node and the second node responsive to an assertion of a write enable signal.

Abstract: A ReRAM memory array includes ReRAM memory cells and a select circuit having two series-connected select transistors connected in series with a ReRAM device. When ReRAM memory cell(s) are selected for erasing, the bit line coupled to the ReRAM memory cell(s) to be erased is biased at a first voltage potential. The source line coupled to the ReRAM memory cell(s) to be erased is biased at a second voltage potential greater than the first voltage potential, the difference between the first voltage potential and the second voltage potential being sufficient to erase the ReRAM device. The gates of the series-connected select transistors coupled to the ReRAM memory cell(s) to be erased are supplied with positive voltage pulses. The gates of the series-connected select transistors coupled to the ReRAM memory cell(s) unselected for erasing are supplied with a voltage potential insufficient to turn them on.

Abstract: A method for erasing a ReRAM memory cell that includes a ReRAM device having a select circuit with two series-connected select transistors. The method includes determining if the ReRAM cell is selected for erasing. If the ReRAM cell is selected for erasing, the bit line node is biased at a first voltage potential, the source line node is biased at a second voltage potential greater than the first voltage potential and the gates of the series-connected select transistors are supplied with positive voltage pulses. The difference between the first voltage potential and the second voltage potential is sufficient to erase the ReRAM device in the ReRAM cell. If the ReRAM cell is unselected for erasing, the gate of the one of the series-connected select transistors having its drain connected to an electrode of the ReRAM device is supplied with a voltage potential insufficient to turn it on.

Abstract: Provided are self-aligned double patterning methods including feature trimming. The SADP process is performed in a single batch processing chamber in which the substrate is laterally moved between sections of the processing chamber separated by gas curtains so that each section independently has a process condition.

Abstract: Provided are self-aligned double patterning methods including feature trimming. The SADP process is performed in a single batch processing chamber in which the substrate is laterally moved between sections of the processing chamber separated by gas curtains so that each section independently has a process condition.

Abstract: Provided are methods for the deposition of films comprising SiCN. Certain methods involve exposing a substrate surface to a silicon precursor, wherein the silicon precursor is halogenated with Cl, Br or I, and the silicon precursor comprises a halogenated silane, a halogenated carbosilane, an halogenated aminosilane or a halogenated carbo-sillyl amine. Then, the substrate surface can be exposed to a nitrogen-containing plasma or a nitrogen precursor and densification plasma.

Abstract: A single-event-upset (SEU) stabilized memory cell includes a latch portion including a cross-coupled latch, and at least one cross coupling circuit path in the latch portion including a first series-connected pair of vertical resistors.

Abstract: A ReRAM memory cell includes a ReRAM device including a solid electrolyte layer disposed between a first ion-source electrode and a second electrode and a select circuit including two series-connected select transistors connected in series with the ReRAM device, each of the two series-connected select transistors having a gate connected to a separate control line.

Abstract: A ReRAM memory cell includes a ReRAM device including a solid electrolyte layer disposed between a first ion-source electrode and a second electrode and a select circuit including two series-connected select transistors connected in series with the ReRAM device, each of the two series-connected select transistors having a gate connected to a separate control line.

Abstract: A method for programming a resistive random-access memory (ReRAM) cell includes passing a first current through the ReRAM device for a first period of time, the first current selected to create a leakage path through the ReRAM device, and after passing the first current through the ReRAM device passing a second current through the ReRAM device for a second period of time shorter than the first period of time, the second current selected to create a current path having a desired resistance through the leakage path through the ReRAM device.

Abstract: A ReRAM memory cell includes a ReRAM device including a solid electrolyte layer disposed between a first ion-source electrode and a second electrode and a select circuit including two series-connected select transistors connected in series with the ReRAM device, each of the two series-connected select transistors having a gate connected to a separate control line.

Abstract: A method for programming a resistive random-access memory (ReRAM) cell includes passing a first current through the ReRAM device for a first period of time, the first current selected to create a leakage path through the ReRAM device, and after passing the first current through the ReRAM device passing a second current through the ReRAM device for a second period of time shorter than the first period of time, the second current selected to create a current path having a desired resistance through the leakage path through the ReRAM device.

Abstract: A single-event-upset (SEU) stabilized memory cell includes a latch portion including a cross-coupled latch, and at least one cross coupling circuit path in the latch portion including a first series-connected pair of vertical resistors.