Abstract: A heat-dissipating fan of the invention has an axle, a bearing, a rotor and a stator. The axle and the bearing are made of a ceramic material, and are located at a central location of the rotor and the stator. The bearing is a hollow cylinder integrally formed into a single body, and has a central hole and a recess at its bottom. The axle penetrates through the central hole of the bearing to contact the recess. A magnetic force center of the silicon steel sheet is at a level lower than that of the magnetic bar to generate radial and axial force components, allowing stable rotation of the rotor. The heat-dissipating fan of the invention provides advantages such as low friction, lower noise, low energy consumption, high performance and high stability.

Abstract: A heat-dissipating fan of the invention has an axle, a bearing, a rotor and a stator. The axle and the bearing are made of a ceramic material, and are located at a central location of the rotor and the stator. The bearing is a hollow cylinder integrally formed into a single body, and has a central hole and a recess at its bottom. The axle penetrates through the central hole of the bearing to contact the recess. A magnetic force center of the silicon steel sheet is at a level lower than that of the magnetic bar to generate radial and axial force components, allowing stable rotation of the rotor. The heat-dissipating fan of the invention provides advantages such as low friction, lower noise, low energy consumption, high performance and high stability.

Abstract: In a floating point addition or subtraction procedure two shift operations of the operand fraction may be required. The first shift operation, based on the difference between the operand exponent arguments, involves aligning one of the operand arguments so that the addition or subtraction procedure between the operand fractions can be performed. In order to complete the associated computations correctly, it is necessary to know if any of the fraction positions removed from the fraction by the shift operation include non-zero signals, i.e., the operation typically referred to as computation of the "sticky" bit. The second important shift operation occurs after the addition or subtraction of the operand fractions has taken place. The interim resulting operand fraction must be normalized, i.e., a non-zero signal is placed in the most significant operand fraction bit position and the operand exponent argument adjusted accordingly.

Abstract: In a multiplier unit implemented with carry/save adder stages and executing a modified Booth algorithm, the signals, required to complete the 2's complement in order to perform a subtraction operation during the multiplication procedure using carry/save adder cells, are entered in the first carry/save stage in the appropriate carry/save cell positions. In this manner, one less signal is processed by the time-critical least significant cell associated with each carry/save adder stage, thereby reducing the overall time delay associated with the multiplier unit and accelerating the multiplication operation.

Abstract: The arithmetic operations performed for floating point format numbers involve procedures having a multiplicity of major steps. In the performance of the effective subtraction operation, the determination of absolute value of the difference between the operand exponent arguments must be obtained in order to determine the correct procedure. In the present invention, a difference between a subset of the operand exponent arguments is calculated and the result of this calculation is used to anticipate the correct procedure. By careful selection of the anticipated correct procedure, when the selection is erroneous, the correct result is immediately available. The availabilty of the correct result is achieved by selecting the subset of operand exponent arguments so that, in the event that the result is erroneous, the correct difference is such that the associated operand fraction (i.e., to be shifted by the amount of the difference) is shifted completely out of the operand fraction field (stored in a register).

Abstract: In a floating point arithmetic execution unit, an additional adder unit and a selection network are added to the apparatus typically performing the arithmetic floating point function. The additional apparatus permits certain processes forming part of arithmetic operations to be executed in parallel. For selected arithmetic operations, the final result can be one of two values typically related by an intermediate shifting operation. By performing the processes in parallel and selecting the appropriate result, the execution time can be reduced when compared to the execution of the process in a serial implementation. The fundamental arithmetic operations of addition, subtraction, multiplication and division can each have the execution time decreased using the disclosed additional apparatus.